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From: Wyes Karny <wyes.karny@amd.com>
To: Rafael J Wysocki <rafael@kernel.org>,
	Huang Rui <ray.huang@amd.com>, Jonathan Corbet <corbet@lwn.net>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	<Mario.Limonciello@amd.com>, <Perry.Yuan@amd.com>
Cc: <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-pm@vger.kernel.org>, Bagas Sanjaya <bagasdotme@gmail.com>,
	<santosh.shukla@amd.com>, Len Brown <lenb@kernel.org>,
	Robert Moore <robert.moore@intel.com>,
	Borislav Petkov <bp@alien8.de>,
	Ananth Narayan <ananth.narayan@amd.com>, <gautham.shenoy@amd.com>,
	Tor Vic <torvic9@mailbox.org>,
	Russell Haley <yumpusamongus@gmail.com>,
	Wyes Karny <wyes.karny@amd.com>,
	Mario Limonciello <mario.limonciello@amd.com>,
	Oleksandr Natalenko <oleksandr@natalenko.name>
Subject: [PATCH v8 1/6] acpi: cppc: Add min and max perf reg writing support
Date: Tue, 7 Mar 2023 11:27:35 +0000	[thread overview]
Message-ID: <20230307112740.132338-2-wyes.karny@amd.com> (raw)
In-Reply-To: <20230307112740.132338-1-wyes.karny@amd.com>

Currently writing of min and max perf register is deferred in
cppc_set_perf function. In CPPC guided mode, these registers needed to
be written to guide the platform about min and max perf levels. Add this support
to make guided mode work properly on AMD shared memory systems.

Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Tested-by: Oleksandr Natalenko <oleksandr@natalenko.name>
Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 drivers/acpi/cppc_acpi.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index c51d3ccb4cca..4fea6b8a26cd 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1488,7 +1488,7 @@ EXPORT_SYMBOL_GPL(cppc_set_enable);
 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 {
 	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
-	struct cpc_register_resource *desired_reg;
+	struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
 	int ret = 0;
@@ -1499,6 +1499,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	}
 
 	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
+	min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
+	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
 
 	/*
 	 * This is Phase-I where we want to write to CPC registers
@@ -1507,7 +1509,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * Since read_lock can be acquired by multiple CPUs simultaneously we
 	 * achieve that goal here
 	 */
-	if (CPC_IN_PCC(desired_reg)) {
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
 		if (pcc_ss_id < 0) {
 			pr_debug("Invalid pcc_ss_id\n");
 			return -ENODEV;
@@ -1530,13 +1532,19 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 		cpc_desc->write_cmd_status = 0;
 	}
 
-	/*
-	 * Skip writing MIN/MAX until Linux knows how to come up with
-	 * useful values.
-	 */
 	cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
 
-	if (CPC_IN_PCC(desired_reg))
+	/**
+	 * Only write if min_perf and max_perf not zero. Some drivers pass zero
+	 * value to min and max perf, but they don't mean to set the zero value,
+	 * they just don't want to write to those registers.
+	 */
+	if (perf_ctrls->min_perf)
+		cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
+	if (perf_ctrls->max_perf)
+		cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
+
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
 		up_read(&pcc_ss_data->pcc_lock);	/* END Phase-I */
 	/*
 	 * This is Phase-II where we transfer the ownership of PCC to Platform
@@ -1584,7 +1592,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * case during a CMD_READ and if there are pending writes it delivers
 	 * the write command before servicing the read command
 	 */
-	if (CPC_IN_PCC(desired_reg)) {
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
 		if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
 			/* Update only if there are pending write commands */
 			if (pcc_ss_data->pending_pcc_write_cmd)
-- 
2.34.1


  reply	other threads:[~2023-03-07 11:28 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-07 11:27 [PATCH v8 0/6] cpufreq: amd-pstate: Add guided autonomous mode support Wyes Karny
2023-03-07 11:27 ` Wyes Karny [this message]
2023-03-07 11:27 ` [PATCH v8 2/6] acpi: cppc: Add auto select register read/write support Wyes Karny
2023-03-07 11:27 ` [PATCH v8 3/6] Documentation: cpufreq: amd-pstate: Move amd_pstate param to alphabetical order Wyes Karny
2023-03-07 11:27 ` [PATCH v8 4/6] cpufreq: amd-pstate: Add guided autonomous mode Wyes Karny
2023-03-07 11:27 ` [PATCH v8 5/6] cpufreq: amd-pstate: Add guided mode control support via sysfs Wyes Karny
2023-03-07 11:27 ` [PATCH v8 6/6] Documentation: cpufreq: amd-pstate: Update amd_pstate status sysfs for guided Wyes Karny
2023-03-17 18:10 ` [PATCH v8 0/6] cpufreq: amd-pstate: Add guided autonomous mode support Rafael J. Wysocki
2023-03-20  4:40   ` Wyes Karny

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