From: Heiko Stuebner <heiko@sntech.de>
To: palmer@rivosinc.com
Cc: greentime.hu@sifive.com, conor@kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
christoph.muellner@vrull.eu, heiko@sntech.de
Subject: [PATCH RFC v3 03/16] RISC-V: add Zbc extension detection
Date: Mon, 13 Mar 2023 20:12:49 +0100 [thread overview]
Message-ID: <20230313191302.580787-4-heiko.stuebner@vrull.eu> (raw)
In-Reply-To: <20230313191302.580787-1-heiko.stuebner@vrull.eu>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
Add handling for Zbc extension.
Zbc provides instruction for carry-less multiplication.
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
arch/riscv/Kconfig | 22 ++++++++++++++++++++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
4 files changed, 25 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index eb691dd8ee4f..8d83935f77d2 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -459,6 +459,28 @@ config RISCV_ISA_ZBB
If you don't know what to do here, say Y.
+config TOOLCHAIN_HAS_ZBC
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc)
+ depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
+ depends on AS_IS_GNU
+
+config RISCV_ISA_ZBC
+ bool "Zbc extension support for bit manipulation instructions"
+ depends on TOOLCHAIN_HAS_ZBC
+ depends on !XIP_KERNEL && MMU
+ default y
+ help
+ Adds support to dynamically detect the presence of the ZBC
+ extension (carry-less multiplication) and enable its usage.
+
+ The Zbc extension provides instructions clmul, clmulh and clmulr
+ to accelerate carry-less multiplications.
+
+ If you don't know what to do here, say Y.
+
config RISCV_ISA_ZICBOM
bool "Zicbom extension support for non-coherent DMA operation"
depends on !XIP_KERNEL && MMU
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index ee73341bb1d4..92f234c6cb4c 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -43,6 +43,7 @@
#define RISCV_ISA_EXT_ZBB 30
#define RISCV_ISA_EXT_ZICBOM 31
#define RISCV_ISA_EXT_ZIHINTPAUSE 32
+#define RISCV_ISA_EXT_ZBC 33
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 8400f0cc9704..5d47a0c75c69 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -188,6 +188,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
+ __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index e6d53e2e672b..c9099694b5bb 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -228,6 +228,7 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
+ SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC);
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
}
--
2.39.0
next prev parent reply other threads:[~2023-03-13 19:13 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-13 19:12 [PATCH RFC v3 00/16] RISC-V: support some cryptography accelerations Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 01/16] riscv: Add support for kernel mode vector Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 02/16] riscv: Add vector extension XOR implementation Heiko Stuebner
2023-03-13 19:12 ` Heiko Stuebner [this message]
2023-03-13 19:12 ` [PATCH RFC v3 04/16] RISC-V: add Zbkb extension detection Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 05/16] RISC-V: hook new crypto subdir into build-system Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 06/16] RISC-V: crypto: add accelerated GCM GHASH implementation Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 07/16] RISC-V: add helper function to read the vector VLEN Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 08/16] RISC-V: add vector crypto extension detection Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 09/16] RISC-V: crypto: update perl include with helpers for vector (crypto) instructions Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 10/16] RISC-V: crypto: add Zvkb accelerated GCM GHASH implementation Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 11/16] RISC-V: crypto: add Zvkg " Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 12/16] RISC-V: crypto: add a vector-crypto-accelerated SHA256 implementation Heiko Stuebner
2023-03-13 19:12 ` [PATCH RFC v3 13/16] RISC-V: crypto: add a vector-crypto-accelerated SHA512 implementation Heiko Stuebner
2023-03-13 19:13 ` [PATCH RFC v3 14/16] RISC-V: crypto: add Zvkned accelerated AES encryption implementation Heiko Stuebner
2023-03-13 19:13 ` [PATCH RFC v3 15/16] RISC-V: crypto: add Zvksed accelerated SM4 " Heiko Stuebner
2023-03-13 19:13 ` [PATCH RFC v3 16/16] RISC-V: crypto: add Zvksh accelerated SM3 hash implementation Heiko Stuebner
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