linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Melissa Wen <mwen@igalia.com>
To: amd-gfx@lists.freedesktop.org,
	Harry Wentland <harry.wentland@amd.com>,
	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
	sunpeng.li@amd.com, Alex Deucher <alexander.deucher@amd.com>,
	dri-devel@lists.freedesktop.org, christian.koenig@amd.com,
	Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch
Cc: Joshua Ashton <joshua@froggi.es>,
	Sebastian Wick <sebastian.wick@redhat.com>,
	Xaver Hugl <xaver.hugl@gmail.com>,
	Shashank Sharma <Shashank.Sharma@amd.com>,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
	sungjoon.kim@amd.com, Alex Hung <alex.hung@amd.com>,
	Melissa Wen <mwen@igalia.com>,
	linux-kernel@vger.kernel.org
Subject: [RFC PATCH 24/40] drm/amd/display: add CRTC 3D LUT support to amd color pipeline
Date: Sun, 23 Apr 2023 13:10:36 -0100	[thread overview]
Message-ID: <20230423141051.702990-25-mwen@igalia.com> (raw)
In-Reply-To: <20230423141051.702990-1-mwen@igalia.com>

Map DRM CRTC 3D LUT in the atomic color mgmt pipeline to DC
(post-blending). 3D LUT works better in a non-linear color space,
therefore using a degamma to linearize the input space may produce
unexpected results. The next patch introduces shaper LUT support that
can be used to delinearize the color space before applying 3D LUT
conversion.

Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   5 +
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 185 +++++++++++++++---
 3 files changed, 174 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6b40e17892e5..760080e4a4da 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9945,7 +9945,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 			DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
 			goto fail;
 		}
-
+#ifdef CONFIG_STEAM_DECK
+		ret = amdgpu_dm_verify_lut3d_size(adev, new_crtc_state);
+		if (ret) {
+			DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
+			goto fail;
+		}
+#endif
 		if (!new_crtc_state->enable)
 			continue;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 5faf4fc87701..b9840c1f3cdf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -894,9 +894,14 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
 
 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
 
+#ifdef CONFIG_STEAM_DECK
 /* 3D LUT max size is 17x17x17 */
 #define MAX_COLOR_3DLUT_ENTRIES 4913
 #define MAX_COLOR_3DLUT_BITDEPTH 12
+int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
+				const struct drm_crtc_state *crtc_state);
+#endif
+
 /* 1D LUT degamma, regamma and shaper*/
 #define MAX_COLOR_LUT_ENTRIES 4096
 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 99b1738c98d3..25010fa19bc8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -332,6 +332,117 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream,
 	return ret;
 }
 
+/**
+ * __set_input_tf - calculates the input transfer function based on expected
+ * input space.
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut.
+ *
+ * Returns:
+ * 0 in case of success. -ENOMEM if fails.
+ */
+static int __set_input_tf(struct dc_transfer_func *func,
+			  const struct drm_color_lut *lut, uint32_t lut_size)
+{
+	struct dc_gamma *gamma = NULL;
+	bool res;
+
+	gamma = dc_create_gamma();
+	if (!gamma)
+		return -ENOMEM;
+
+	gamma->type = GAMMA_CUSTOM;
+	gamma->num_entries = lut_size;
+
+	__drm_lut_to_dc_gamma(lut, gamma, false);
+
+	res = mod_color_calculate_degamma_params(NULL, func, gamma, true);
+	dc_gamma_release(&gamma);
+
+	return res ? 0 : -ENOMEM;
+}
+
+#ifdef CONFIG_STEAM_DECK
+static void __to_dc_lut3d_color(struct dc_rgb *rgb,
+				const struct drm_color_lut lut,
+				int bit_precision)
+{
+	rgb->red = drm_color_lut_extract(lut.red, bit_precision);
+	rgb->green = drm_color_lut_extract(lut.green, bit_precision);
+	rgb->blue  = drm_color_lut_extract(lut.blue, bit_precision);
+}
+
+static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut,
+				    uint32_t lut3d_size,
+				    struct tetrahedral_params *params,
+				    bool use_tetrahedral_9,
+				    int bit_depth)
+{
+	struct dc_rgb *lut0;
+	struct dc_rgb *lut1;
+	struct dc_rgb *lut2;
+	struct dc_rgb *lut3;
+	int lut_i, i;
+
+
+	if (use_tetrahedral_9) {
+		lut0 = params->tetrahedral_9.lut0;
+		lut1 = params->tetrahedral_9.lut1;
+		lut2 = params->tetrahedral_9.lut2;
+		lut3 = params->tetrahedral_9.lut3;
+	} else {
+		lut0 = params->tetrahedral_17.lut0;
+		lut1 = params->tetrahedral_17.lut1;
+		lut2 = params->tetrahedral_17.lut2;
+		lut3 = params->tetrahedral_17.lut3;
+	}
+
+	for (lut_i = 0, i = 0; i < lut3d_size - 4; lut_i++, i += 4) {
+		/* We should consider the 3dlut RGB values are distributed
+		 * along four arrays lut0-3 where the first sizes 1229 and the
+		 * other 1228. The bit depth supported for 3dlut channel is
+		 * 12-bit, but DC also supports 10-bit.
+		 *
+		 * TODO: improve color pipeline API to enable the userspace set
+		 * bit depth and 3D LUT size/stride, as specified by VA-API.
+		 */
+		__to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth);
+		__to_dc_lut3d_color(&lut1[lut_i], lut[i + 1], bit_depth);
+		__to_dc_lut3d_color(&lut2[lut_i], lut[i + 2], bit_depth);
+		__to_dc_lut3d_color(&lut3[lut_i], lut[i + 3], bit_depth);
+	}
+	/* lut0 has 1229 points (lut_size/4 + 1) */
+	__to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth);
+}
+
+/* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream
+ * @drm_lut3d: DRM CRTC (user) 3D LUT
+ * @drm_lut3d_size: size of 3D LUT
+ * @lut3d: DC 3D LUT
+ *
+ * Map DRM CRTC 3D LUT to DC 3D LUT and all necessary bits to program it
+ * on DCN MPC accordingly.
+ */
+static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut,
+				   uint32_t drm_lut3d_size,
+				   struct dc_3dlut *lut)
+{
+	if (!drm_lut3d_size) {
+		lut->state.bits.initialized = 0;
+	} else {
+		/* Stride and bit depth are not programmable by API yet.
+		 * Therefore, only supports 17x17x17 3D LUT (12-bit).
+		 */
+		lut->lut_3d.use_tetrahedral_9 = false;
+		lut->lut_3d.use_12bits = true;
+		lut->state.bits.initialized = 1;
+		__drm_3dlut_to_dc_3dlut(drm_lut, drm_lut3d_size, &lut->lut_3d,
+					lut->lut_3d.use_tetrahedral_9,
+					MAX_COLOR_3DLUT_BITDEPTH);
+	}
+}
+
 /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC
  * interface
  * @dc: Display Core control structure
@@ -355,7 +466,7 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc,
 {
 	struct dc_3dlut *lut3d_func;
 	struct dc_transfer_func *func_shaper;
-	bool acquire = drm_shaper_size && drm_lut3d_size;
+	bool acquire = drm_shaper_size || drm_lut3d_size;
 
 	lut3d_func = (struct dc_3dlut *)stream->lut3d_func;
 	func_shaper = (struct dc_transfer_func *)stream->func_shaper;
@@ -369,42 +480,56 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc,
 			return DC_ERROR_UNEXPECTED;
 	}
 
-	stream->lut3d_func = lut3d_func;
 	stream->func_shaper = func_shaper;
+	stream->lut3d_func = lut3d_func;
+
+	if (!acquire)
+		return 0;
+
+	/* We don't get DRM shaper LUT yet. We assume the input color
+	 * space is already delinearized, so we don't need a shaper LUT
+	 * and we can just BYPASS.
+	 */
+	func_shaper->type = TF_TYPE_BYPASS;
+	func_shaper->tf = TRANSFER_FUNCTION_LINEAR;
+	amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func);
 
 	return 0;
 }
 
 /**
- * __set_input_tf - calculates the input transfer function based on expected
- * input space.
- * @func: transfer function
- * @lut: lookup table that defines the color space
- * @lut_size: size of respective lut.
+ * amdgpu_dm_verify_lut3d_size - verifies if 3D LUT is supported and if DRM 3D
+ * LUT matches the hw supported size
+ * @adev: amdgpu device
+ * @crtc_state: the DRM CRTC state
+ *
+ * Verifies if post-blending (MPC) 3D LUT is supported by the HW (DCN 3.0 or
+ * newer) and if the DRM 3D LUT matches the supported size.
  *
  * Returns:
- * 0 in case of success. -ENOMEM if fails.
+ * 0 on success. -EINVAL if lut size are invalid.
  */
-static int __set_input_tf(struct dc_transfer_func *func,
-			  const struct drm_color_lut *lut, uint32_t lut_size)
+int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
+				const struct drm_crtc_state *crtc_state)
 {
-	struct dc_gamma *gamma = NULL;
-	bool res;
+	const struct drm_color_lut *lut3d = NULL;
+	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc_state);
+	uint32_t exp_size, size;
 
-	gamma = dc_create_gamma();
-	if (!gamma)
-		return -ENOMEM;
+	exp_size = adev->dm.dc->caps.color.mpc.num_3dluts ?
+		   MAX_COLOR_3DLUT_ENTRIES : 0;
 
-	gamma->type = GAMMA_CUSTOM;
-	gamma->num_entries = lut_size;
-
-	__drm_lut_to_dc_gamma(lut, gamma, false);
+	lut3d = __extract_blob_lut(acrtc_state->lut3d, &size);
 
-	res = mod_color_calculate_degamma_params(NULL, func, gamma, true);
-	dc_gamma_release(&gamma);
+	if (lut3d && size != exp_size) {
+		DRM_DEBUG_DRIVER("Invalid Gamma 3D LUT size. Should be %u but got %u.\n",
+				 exp_size, size);
+		return -EINVAL;
+	}
 
-	return res ? 0 : -ENOMEM;
+	return 0;
 }
+#endif
 
 /**
  * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes
@@ -477,6 +602,16 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc,
 	bool has_regamma, has_degamma;
 	bool is_legacy;
 	int r;
+#ifdef CONFIG_STEAM_DECK
+	const struct drm_color_lut *lut3d;
+	uint32_t lut3d_size;
+
+	r =  amdgpu_dm_verify_lut3d_size(adev, &crtc->base);
+	if (r)
+		return r;
+
+	lut3d = __extract_blob_lut(crtc->lut3d, &lut3d_size);
+#endif
 
 	r = amdgpu_dm_verify_lut_sizes(&crtc->base);
 	if (r)
@@ -525,10 +660,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc,
 		if (r)
 			return r;
 	} else {
+#ifdef CONFIG_STEAM_DECK
+		lut3d_size = lut3d != NULL ? lut3d_size : 0;
 		r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream,
-						  NULL, 0, NULL, 0);
+						  NULL, 0,
+						  lut3d, lut3d_size);
 		if (r)
 			return r;
+#endif
 		/* Note: OGAM is disabled if 3D LUT is successfully programmed.
 		 * See params and set_output_gamma in
 		 * dcn30_set_output_transfer_func()
-- 
2.39.2


  parent reply	other threads:[~2023-04-23 14:15 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-23 14:10 [RFC PATCH 00/40] drm/amd/display: add AMD driver-specific properties for color mgmt Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 01/40] drm/amd/display: fix segment distribution for linear LUTs Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 02/40] drm/amd/display: fix the delta clamping for shaper LUT Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 03/40] drm/amd/display: introduce Steam Deck color features to AMD display driver Melissa Wen
2023-05-08 21:24   ` Harry Wentland
2023-05-09 16:23     ` Melissa Wen
2023-05-09 16:52       ` Joshua Ashton
2023-05-09 17:19         ` Harry Wentland
2023-05-09 17:20       ` Harry Wentland
2023-04-23 14:10 ` [RFC PATCH 04/40] drm/drm_mode_object: increase max objects to accommodate new color props Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 05/40] drm/amd/display: add shaper LUT driver-private props Melissa Wen
2023-05-08 21:24   ` Harry Wentland
2023-05-09 16:30     ` Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 06/40] drm/amd/display: add 3D " Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 07/40] drm/amd/display: add CRTC gamma TF to " Melissa Wen
2023-05-08 21:24   ` Harry Wentland
2023-05-09 16:34     ` Melissa Wen
2023-05-09 16:55       ` Joshua Ashton
2023-04-23 14:10 ` [RFC PATCH 08/40] drm/drm_plane: track color mgmt changes per plane Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 09/40] drm/amd/display: move replace blob func to dm plane Melissa Wen
2023-05-08 21:24   ` Harry Wentland
2023-05-09 16:35     ` Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 10/40] drm/amd/display: add plane degamma LUT driver-private props Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 11/40] drm/amd/display: add plane degamma TF driver-private property Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 12/40] drm/amd/display: add plane HDR multiplier " Melissa Wen
2023-05-08 21:24   ` Harry Wentland
2023-05-09 16:37     ` Melissa Wen
2023-05-09 16:54       ` Joshua Ashton
2023-05-09 20:00         ` Harry Wentland
2023-05-09 20:35           ` Joshua Ashton
2023-05-09 22:55             ` Harry Wentland
2023-04-23 14:10 ` [RFC PATCH 13/40] drm/amd/display: add plane 3D LUT driver-private properties Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 14/40] drm/amd/display: add plane shaper " Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 15/40] drm/amd/display: add plane shaper TF driver-private property Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 16/40] drm/amd/display: add plane blend LUT and TF driver-private properties Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 17/40] drm/amd/display: add comments to describe DM crtc color mgmt behavior Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 18/40] drm/amd/display: encapsulate atomic regamma operation Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 19/40] drm/amd/display: update lut3d and shaper lut to stream Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 20/40] drm/amd/display: copy 3D LUT settings from crtc state to stream_update Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 21/40] drm/amd/display: allow BYPASS 3D LUT but keep shaper LUT settings Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 22/40] drm/amd/display: handle MPC 3D LUT resources for a given context Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 23/40] drm/amd/display: dynamically acquire 3DLUT resources for color changes Melissa Wen
2023-04-23 14:10 ` Melissa Wen [this message]
2023-04-23 14:10 ` [RFC PATCH 25/40] drm/amd/display: decouple steps to reuse in CRTC shaper LUT support Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 26/40] drm/amd/display: add CRTC shaper LUT support to amd color pipeline Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 27/40] drm/amd/display: add CRTC regamma TF support Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 28/40] drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_func Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 29/40] drm/amd/display: add CRTC shaper TF support Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 30/40] drm/amd/display: mark plane as needing reset if plane color mgmt changes Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 31/40] drm/amd/display: decouple steps for mapping CRTC degamma to DC plane Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 32/40] drm/amd/display: add support for plane degamma TF and LUT properties Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 33/40] drm/amd/display: reject atomic commit if setting both plane and CRTC degamma Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 34/40] drm/amd/display: add dc_fixpt_from_s3132 helper Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 35/40] drm/adm/display: add HDR multiplier support Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 36/40] drm/amd/display: add plane shaper/3D LUT and shaper TF support Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 37/40] drm/amd/display: handle empty LUTs in __set_input_tf Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 38/40] drm/amd/display: add DRM plane blend LUT and TF support Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 39/40] drm/amd/display: copy dc_plane color settings to surface_updates Melissa Wen
2023-04-23 14:10 ` [RFC PATCH 40/40] drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLG Melissa Wen
2023-05-08 21:24 ` [RFC PATCH 00/40] drm/amd/display: add AMD driver-specific properties for color mgmt Harry Wentland
2023-05-09 16:52   ` Melissa Wen
2023-05-09 17:25     ` Harry Wentland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230423141051.702990-25-mwen@igalia.com \
    --to=mwen@igalia.com \
    --cc=Rodrigo.Siqueira@amd.com \
    --cc=Shashank.Sharma@amd.com \
    --cc=Xinhui.Pan@amd.com \
    --cc=airlied@gmail.com \
    --cc=alex.hung@amd.com \
    --cc=alexander.deucher@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=christian.koenig@amd.com \
    --cc=daniel@ffwll.ch \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=harry.wentland@amd.com \
    --cc=joshua@froggi.es \
    --cc=linux-kernel@vger.kernel.org \
    --cc=nicholas.kazlauskas@amd.com \
    --cc=sebastian.wick@redhat.com \
    --cc=sungjoon.kim@amd.com \
    --cc=sunpeng.li@amd.com \
    --cc=xaver.hugl@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).