From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74B87C77B7C for ; Wed, 10 May 2023 13:42:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237181AbjEJNmV (ORCPT ); Wed, 10 May 2023 09:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237162AbjEJNmQ (ORCPT ); Wed, 10 May 2023 09:42:16 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B9286A52; Wed, 10 May 2023 06:42:15 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34AD7udc020379; Wed, 10 May 2023 13:42:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=AM5hRRVid6vttUj2gZ9JrIaCq684VKKdQ2gLLKXG9DY=; b=X+2jx2h87H/au5bMtx+zTBbHpZfxW9oqlOL24zL9An46qzAef52uklbPiNIJVz4wQfxs 9XkDOUQQ1HVJBrDF7ONewVGi5MRYyHihTMM7tu8l0aNyO8w+hTXugXPN1dqVRq+xY9TQ wumyn0fsPjPB+Yrd2pjXkrAkDowtTLDGxXQpBjYAF6f8jzoSJbgrPDRZIxa5rKi2J+DQ Pxt8s/WwVpdPYicsoVCdPAitMkTcWbQG/C4WQgJSr+c16fXq2oDxC8VRNE6sY0XXiLP+ 7gNj+4EmpxtsZFiYXl6AV4w1rpzr/5L2D093wj59Wl2Ugeaei2csQ7EGkrUuJa6dl+gU 2A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qg79crkdw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 May 2023 13:42:05 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34ADfe5L010514 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 May 2023 13:41:40 GMT Received: from win-platform-upstream01.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 10 May 2023 06:41:35 -0700 From: Sricharan Ramabadhran To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 0/8] Add minimal boot support for IPQ5018 Date: Wed, 10 May 2023 19:11:13 +0530 Message-ID: <20230510134121.1232286-1-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yvgwojd-irm1kv0FpNAtkEPvj4JtZcd2 X-Proofpoint-ORIG-GUID: yvgwojd-irm1kv0FpNAtkEPvj4JtZcd2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-10_04,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 mlxscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 mlxlogscore=748 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305100109 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The IPQ5018 is Qualcomm's 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq5018-mp03.1-c2 board. [v4] Fixed all comments for clocks, schema, dts Added Reviewed-by tags. [v3] Fixed all comments for clocks, schema fixes Picked up Reviewed-by from Bjorn for pinctrl driver [v2] Fixed all comments and rebased for TOT. Sricharan Ramabadhran (8): dt-bindings: arm64: Add IPQ5018 clock and reset clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 dt-bindings: pinctrl: qcom: Add support for ipq5018 pinctrl: qcom: Add IPQ5018 pinctrl driver dt-bindings: qcom: Add ipq5018 bindings dt-bindings: firmware: document IPQ5018 SCM arm64: dts: Add ipq5018 SoC and rdp432-c2 board support arm64: defconfig: Enable IPQ5018 SoC base configs .../devicetree/bindings/arm/qcom.yaml | 7 + .../bindings/clock/qcom,ipq5018-gcc.yaml | 63 + .../bindings/firmware/qcom,scm.yaml | 1 + .../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 + arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++ arch/arm64/configs/defconfig | 3 + drivers/clk/qcom/Kconfig | 10 +- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5018.c | 3731 +++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5018.c | 791 ++++ include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 + include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 + 16 files changed, 5371 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq5018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h -- 2.34.1