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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:00 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 25/30] net: dsa: mt7530: properly set MT7531_CPU_PMAP Date: Mon, 22 May 2023 15:15:27 +0300 Message-Id: <20230522121532.86610-26-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arınç ÜNAL Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. Currently only the bit that corresponds to the first found CPU port is set on the bitmap. Introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add comments to explain this. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 15 ++++++++------- drivers/net/dsa/mt7530.h | 3 ++- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 58d8738d94d3..0b513e3628fe 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -963,6 +963,13 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_MASK, MT7530_CPU_EN | MT7530_CPU_PORT(port)); + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Any frames set for trapping to CPU port will be + * trapped to the CPU port the user port is affine to. + */ + if (priv->id == ID_MT7531 || priv->id == ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2315,15 +2322,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; - struct dsa_port *cpu_dp; int ret, i; - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5ebb942b07ef..fd2a2f726b8a 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -53,7 +53,8 @@ enum mt753x_id { #define MT7531_MIRROR_MASK (0x7 << 16) #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & 0x7) #define MT7531_MIRROR_PORT_SET(x) (((x) & 0x7) << 16) -#define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) ((x) & 0xff) +#define MT7531_CPU_PMAP_MASK MT7531_CPU_PMAP(~0) #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ MT7531_CFC : MT753X_MFC) -- 2.39.2