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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT018.mail.protection.outlook.com (10.13.172.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.28 via Frontend Transport; Mon, 22 May 2023 12:28:45 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 22 May 2023 07:28:43 -0500 Received: from xhdharinik40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 22 May 2023 07:28:39 -0500 From: Harini Katakam To: , , , , , , , , , CC: , , , , , Subject: [PATCH net-next v4 2/2] phy: mscc: Add support for RGMII delay configuration Date: Mon, 22 May 2023 17:58:29 +0530 Message-ID: <20230522122829.24945-3-harini.katakam@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230522122829.24945-1-harini.katakam@amd.com> References: <20230522122829.24945-1-harini.katakam@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT018:EE_|DM8PR12MB5480:EE_ X-MS-Office365-Filtering-Correlation-Id: 0577aaf5-bab9-4261-909d-08db5ac0163a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2023 12:28:45.5277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0577aaf5-bab9-4261-909d-08db5ac0163a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5480 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for optional rx/tx-internal-delay-ps from devicetree. - When rx/tx-internal-delay-ps is/are specified, these take priority - When either is absent, 1) use 2ns for respective settings if rgmii-id/rxid/txid is/are present 2) use 0.2ns for respective settings if mode is rgmii Signed-off-by: Harini Katakam --- v4: Fix type of rx_delay and tx_delay Reported by Simon Horman and Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202305140248.lh4LUw2j-lkp@intel.com/ v3 - Patch split: - Use rx/tx-internal-delay-ps with phy_get_internal_delay - Change RGMII delay selection precedence - Update commit description and subject everywhere to say RGMII delays instead of RGMII tuning. drivers/net/phy/mscc/mscc.h | 2 ++ drivers/net/phy/mscc/mscc_main.c | 35 +++++++++++++++++++++++++------- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 9acee8759105..900bf37db9de 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -374,6 +374,8 @@ struct vsc8531_private { * package. */ unsigned int base_addr; + s32 rx_delay; + s32 tx_delay; #if IS_ENABLED(CONFIG_MACSEC) /* MACsec fields: diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 91010524e03d..9e856231e464 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -525,17 +525,14 @@ static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, { u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1; u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1; + struct vsc8531_private *vsc8531 = phydev->priv; u16 reg_val = 0; int rc; mutex_lock(&phydev->lock); - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos; + reg_val |= vsc8531->rx_delay << rgmii_rx_delay_pos; + reg_val |= vsc8531->tx_delay << rgmii_tx_delay_pos; rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, rgmii_cntl, @@ -1808,10 +1805,34 @@ static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) return IRQ_HANDLED; } +static const int vsc8531_internal_delay[] = {200, 800, 1100, 1700, 2000, 2300, + 2600, 3400}; static int vsc85xx_config_init(struct phy_device *phydev) { - int rc, i, phy_id; + int delay_size = ARRAY_SIZE(vsc8531_internal_delay); struct vsc8531_private *vsc8531 = phydev->priv; + struct device *dev = &phydev->mdio.dev; + int rc, i, phy_id; + + vsc8531->rx_delay = phy_get_internal_delay(phydev, dev, &vsc8531_internal_delay[0], + delay_size, true); + if (vsc8531->rx_delay < 0) { + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + vsc8531->rx_delay = RGMII_CLK_DELAY_2_0_NS; + else + vsc8531->rx_delay = RGMII_CLK_DELAY_0_2_NS; + } + + vsc8531->tx_delay = phy_get_internal_delay(phydev, dev, &vsc8531_internal_delay[0], + delay_size, false); + if (vsc8531->tx_delay < 0) { + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + vsc8531->rx_delay = RGMII_CLK_DELAY_2_0_NS; + else + vsc8531->rx_delay = RGMII_CLK_DELAY_0_2_NS; + } rc = vsc85xx_default_config(phydev); if (rc) -- 2.17.1