From: Sascha Hauer <s.hauer@pengutronix.de>
To: linux-rockchip@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Heiko Stuebner <heiko@sntech.de>,
Kyungmin Park <kyungmin.park@samsung.com>,
MyungJoo Ham <myungjoo.ham@samsung.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
kernel@pengutronix.de,
Michael Riesch <michael.riesch@wolfvision.net>,
Robin Murphy <robin.murphy@arm.com>,
Vincent Legoll <vincent.legoll@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Sascha Hauer <s.hauer@pengutronix.de>
Subject: [PATCH v5 09/25] PM / devfreq: rockchip-dfi: Clean up DDR type register defines
Date: Wed, 24 May 2023 10:31:37 +0200 [thread overview]
Message-ID: <20230524083153.2046084-10-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20230524083153.2046084-1-s.hauer@pengutronix.de>
Use the HIWORD_UPDATE() define known from other rockchip drivers to
make the defines look less odd to the readers who've seen other
rockchip drivers.
The HIWORD registers have their functional bits in the lower 16 bits
whereas the upper 16 bits contain a mask. Only the functional bits that
have the corresponding mask bit set are modified during a write. Although
the register writes look different, the end result should be the same,
at least there's no functional change intended with this patch.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/devfreq/event/rockchip-dfi.c | 33 ++++++++++++++++++----------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 6bccb6fbcfc0c..6b3ef97b3be09 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -26,15 +26,19 @@
#define DMC_MAX_CHANNELS 2
+#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
+
/* DDRMON_CTRL */
#define DDRMON_CTRL 0x04
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
-#define LPDDR4_EN (0x10001 << 4)
-#define HARDWARE_EN (0x10001 << 3)
-#define LPDDR3_EN (0x10001 << 2)
-#define SOFTWARE_EN (0x10001 << 1)
-#define SOFTWARE_DIS (0x10000 << 1)
-#define TIME_CNT_EN (0x10001 << 0)
+#define DDRMON_CTRL_DDR4 BIT(5)
+#define DDRMON_CTRL_LPDDR4 BIT(4)
+#define DDRMON_CTRL_HARDWARE_EN BIT(3)
+#define DDRMON_CTRL_LPDDR23 BIT(2)
+#define DDRMON_CTRL_SOFTWARE_EN BIT(1)
+#define DDRMON_CTRL_TIMER_CNT_EN BIT(0)
+#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \
+ DDRMON_CTRL_LPDDR4 | \
+ DDRMON_CTRL_LPDDR23)
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
@@ -73,16 +77,20 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
void __iomem *dfi_regs = dfi->regs;
/* clear DDRMON_CTRL setting */
- writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
+ DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
+ dfi_regs + DDRMON_CTRL);
else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
- writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
+ dfi_regs + DDRMON_CTRL);
/* enable count, use software mode */
- writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
+ dfi_regs + DDRMON_CTRL);
}
static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
@@ -90,7 +98,8 @@ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = dfi->regs;
- writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+ dfi_regs + DDRMON_CTRL);
}
static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
--
2.39.2
next prev parent reply other threads:[~2023-05-24 8:34 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-24 8:31 [PATCH v5 00/25] Add perf support to the rockchip-dfi driver Sascha Hauer
2023-05-24 8:31 ` [PATCH v5 01/25] PM / devfreq: rockchip-dfi: Make pmu regmap mandatory Sascha Hauer
2023-06-13 16:21 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 02/25] PM / devfreq: rockchip-dfi: Embed desc into private data struct Sascha Hauer
2023-06-13 16:22 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 03/25] PM / devfreq: rockchip-dfi: use consistent name for " Sascha Hauer
2023-06-13 16:23 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 04/25] PM / devfreq: rockchip-dfi: Add SoC specific init function Sascha Hauer
2023-06-13 16:26 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 05/25] PM / devfreq: rockchip-dfi: dfi store raw values in counter struct Sascha Hauer
2023-06-13 16:28 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 06/25] PM / devfreq: rockchip-dfi: Use free running counter Sascha Hauer
2023-06-13 16:32 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 07/25] PM / devfreq: rockchip-dfi: introduce channel mask Sascha Hauer
2023-06-13 16:34 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 08/25] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines Sascha Hauer
2023-06-13 16:39 ` Sebastian Reichel
2023-05-24 8:31 ` Sascha Hauer [this message]
2023-06-13 16:46 ` [PATCH v5 09/25] PM / devfreq: rockchip-dfi: Clean up DDR type register defines Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 10/25] PM / devfreq: rockchip-dfi: Add RK3568 support Sascha Hauer
2023-05-24 8:31 ` [PATCH v5 11/25] PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly Sascha Hauer
2023-06-13 16:47 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 12/25] PM / devfreq: rockchip-dfi: Handle LPDDR4X Sascha Hauer
2023-06-13 16:48 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 13/25] PM / devfreq: rockchip-dfi: Pass private data struct to internal functions Sascha Hauer
2023-06-13 17:08 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 14/25] PM / devfreq: rockchip-dfi: Prepare for multiple users Sascha Hauer
2023-06-13 17:15 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 15/25] PM / devfreq: rockchip-dfi: give variable a better name Sascha Hauer
2023-06-13 17:16 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 16/25] PM / devfreq: rockchip-dfi: Add perf support Sascha Hauer
2023-06-14 13:29 ` Sebastian Reichel
2023-06-15 13:13 ` Sascha Hauer
2023-05-24 8:31 ` [PATCH v5 17/25] PM / devfreq: rockchip-dfi: make register stride SoC specific Sascha Hauer
2023-06-13 17:17 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 18/25] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers Sascha Hauer
2023-06-13 17:24 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 19/25] PM / devfreq: rockchip-dfi: add support for RK3588 Sascha Hauer
2023-06-13 16:16 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 20/25] dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml Sascha Hauer
2023-06-13 23:39 ` Sebastian Reichel
2023-05-24 8:31 ` [PATCH v5 21/25] dt-bindings: devfreq: event: rockchip,dfi: Add rk3568 support Sascha Hauer
2023-05-24 19:42 ` Conor Dooley
2023-05-24 8:31 ` [PATCH v5 22/25] dt-bindings: devfreq: event: rockchip,dfi: Add rk3588 support Sascha Hauer
2023-05-24 19:37 ` Conor Dooley
2023-06-08 20:07 ` Rob Herring
2023-05-24 8:31 ` [PATCH v5 23/25] arm64: dts: rockchip: rk3399: Enable DFI Sascha Hauer
2023-05-24 8:31 ` [PATCH v5 24/25] arm64: dts: rockchip: rk356x: Add DFI Sascha Hauer
2023-05-24 8:31 ` [PATCH v5 25/25] arm64: dts: rockchip: rk3588s: " Sascha Hauer
2023-06-13 16:19 ` Sebastian Reichel
2023-06-14 13:40 ` [PATCH v5 00/25] Add perf support to the rockchip-dfi driver Sebastian Reichel
2023-06-14 14:19 ` Vincent Legoll
2023-06-14 15:27 ` Sebastian Reichel
2023-06-14 19:51 ` Vincent Legoll
2023-06-14 22:18 ` Sebastian Reichel
2023-06-15 6:56 ` Sascha Hauer
2023-06-15 13:27 ` Sascha Hauer
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