From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9638FC77B73 for ; Tue, 6 Jun 2023 09:58:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236943AbjFFJ61 (ORCPT ); Tue, 6 Jun 2023 05:58:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236970AbjFFJ6U (ORCPT ); Tue, 6 Jun 2023 05:58:20 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E89F210F2; Tue, 6 Jun 2023 02:58:09 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3566f70r018590; Tue, 6 Jun 2023 09:58:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=k4qCw/xNHwNtKcdRQNUTH/pfdWG3pyOk5FKCOUcEiCc=; b=ICGihW2zYJ9FnhDWrgbTrl2GLy/H+U8SIwYNdt0t3a2G6Qnuz4vWP+j+ifqfDSUlaAHc vKb/2PfgfDhEwimho2s20lLy1TmrF8vgS+u1/X3QZki4X+Vmu4Gd0xEn0hj8oZciHuwD aAVQnHOiMOem8ccUVv58t556BpMR+owchSwfIp4Pa8eY4lomeRH8nndGHFRoEczJI2xh aowIp5EtxSVUfsOdvHXtNTbNYzh4Gr+KRKeANcFRiazmHQc+I9gBBt9eAHTZgqNKjfj2 hqrvMifoPpT8oVGD5Hpt3DQJFgBjFI7IbZHOpirw+UTsQMmUKai4NzMye2sGQO1NT3nt +A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r1jg3huvc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Jun 2023 09:58:06 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3569w5c7022087 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Jun 2023 09:58:05 GMT Received: from harihk-linux.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 6 Jun 2023 02:58:00 -0700 From: Hariharan K To: , , , , , , , , CC: , , , , Subject: [PATCH 2/2] arm64: dts: qcom: ipq5332: add support for the RDP446 variant Date: Tue, 6 Jun 2023 15:27:32 +0530 Message-ID: <20230606095732.12884-3-quic_harihk@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230606095732.12884-1-quic_harihk@quicinc.com> References: <20230606095732.12884-1-quic_harihk@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dEQ6wCbNvyjs8vK4eucgaEPJ86M0NyWi X-Proofpoint-ORIG-GUID: dEQ6wCbNvyjs8vK4eucgaEPJ86M0NyWi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-06_06,2023-06-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306060084 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the initial device tree support for the Reference Design Platform(RDP) 446 based on IPQ5332 family of SoC. This patch carries the support for Console UART, SPI NOR and I2C. Signed-off-by: Hariharan K --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts | 83 +++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4f9e81253e18..f962e1b7cf7a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp446.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts new file mode 100644 index 000000000000..0e1d98b093e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 AP-MI04.1 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI04.1"; + compatible = "qcom,ipq5332-ap-mi04.1", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + spi_0_data_clk_pins: spi-0-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-down; + }; + + spi_0_cs_pins: spi-0-cs-state { + pins = "gpio17"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-up; + }; +}; -- 2.17.1