From: Rob Herring <robh@kernel.org>
To: Lizhi Hou <lizhi.hou@amd.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, max.zhen@amd.com,
sonal.santan@amd.com, stefano.stabellini@xilinx.com
Subject: Re: [PATCH V9 4/6] PCI: Add ranges property for pci endpoint
Date: Tue, 20 Jun 2023 16:00:31 -0600 [thread overview]
Message-ID: <20230620220031.GA384833-robh@kernel.org> (raw)
In-Reply-To: <1686847842-33780-5-git-send-email-lizhi.hou@amd.com>
On Thu, Jun 15, 2023 at 09:50:40AM -0700, Lizhi Hou wrote:
> For PCI endpoint defined quirks to generate device tree node, it requires
> 'ranges' property to translate iomem addresses for its downstream devices.
I'm not following why this patch is separate from patch 2 nor how patch
3 would function without it.
>
> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
> ---
> drivers/pci/of_property.c | 33 ++++++++++++++++++++++-----------
> drivers/pci/quirks.c | 1 +
> 2 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/of_property.c b/drivers/pci/of_property.c
> index bdd756c8d7de..08654740f314 100644
> --- a/drivers/pci/of_property.c
> +++ b/drivers/pci/of_property.c
> @@ -84,15 +84,22 @@ static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs,
> struct of_pci_range *rp;
> struct resource *res;
> int i = 0, j, ret;
> + u32 flags, num;
> u64 val64;
> - u32 flags;
>
> - rp = kcalloc(PCI_BRIDGE_RESOURCE_NUM, sizeof(*rp), GFP_KERNEL);
> + if (pci_is_bridge(pdev)) {
> + num = PCI_BRIDGE_RESOURCE_NUM;
> + res = &pdev->resource[PCI_BRIDGE_RESOURCES];
> + } else {
> + num = PCI_STD_NUM_BARS;
> + res = &pdev->resource[PCI_STD_RESOURCES];
> + }
> +
> + rp = kcalloc(num, sizeof(*rp), GFP_KERNEL);
> if (!rp)
> return -ENOMEM;
>
> - res = &pdev->resource[PCI_BRIDGE_RESOURCES];
> - for (j = 0; j < PCI_BRIDGE_RESOURCE_NUM; j++) {
> + for (j = 0; j < num; j++) {
> if (!resource_size(&res[j]))
> continue;
>
> @@ -102,8 +109,12 @@ static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs,
> val64 = res[j].start;
> of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags,
> false);
> - memcpy(rp[i].child_addr, rp[i].parent_addr,
> - sizeof(rp[i].child_addr));
> + if (pci_is_bridge(pdev)) {
> + memcpy(rp[i].child_addr, rp[i].parent_addr,
> + sizeof(rp[i].child_addr));
> + } else {
> + rp[i].child_addr[0] = j;
A comment that child address lower 64-bits is always 0x0 would be
helpful here.
> + }
>
> val64 = resource_size(&res[j]);
> rp[i].size[0] = upper_32_bits(val64);
> @@ -161,13 +172,13 @@ int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
> if (pci_is_bridge(pdev)) {
> ret |= of_changeset_add_prop_string(ocs, np, "device_type",
> "pci");
> - ret |= of_changeset_add_prop_u32(ocs, np, "#address-cells",
> - OF_PCI_ADDRESS_CELLS);
> - ret |= of_changeset_add_prop_u32(ocs, np, "#size-cells",
> - OF_PCI_SIZE_CELLS);
> - ret |= of_pci_prop_ranges(pdev, ocs, np);
> }
>
> + ret |= of_pci_prop_ranges(pdev, ocs, np);
> + ret |= of_changeset_add_prop_u32(ocs, np, "#address-cells",
> + OF_PCI_ADDRESS_CELLS);
> + ret |= of_changeset_add_prop_u32(ocs, np, "#size-cells",
> + OF_PCI_SIZE_CELLS);
> ret |= of_pci_prop_reg(pdev, ocs, np);
> ret |= of_pci_prop_compatible(pdev, ocs, np);
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index c8f3acea752d..51945b631628 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -6052,3 +6052,4 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
> */
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-06-20 22:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 16:50 [PATCH V9 0/6] Generate device tree node for pci devices Lizhi Hou
2023-06-15 16:50 ` [PATCH V9 1/6] of: dynamic: Add interfaces for creating device node dynamically Lizhi Hou
2023-06-15 16:50 ` [PATCH V9 2/6] PCI: Create device tree node for selected devices Lizhi Hou
2023-06-15 16:50 ` [PATCH V9 3/6] PCI: Add PCI quirks to generate device tree node for Xilinx Alveo U50 Lizhi Hou
2023-06-15 16:50 ` [PATCH V9 4/6] PCI: Add ranges property for pci endpoint Lizhi Hou
2023-06-20 22:00 ` Rob Herring [this message]
2023-06-20 22:57 ` Lizhi Hou
2023-06-15 16:50 ` [PATCH V9 5/6] of: overlay: Extend of_overlay_fdt_apply() to specify the target node Lizhi Hou
2023-06-15 16:50 ` [PATCH V9 6/6] of: unittest: Add pci_dt_testdrv pci driver Lizhi Hou
2023-06-15 20:58 ` kernel test robot
2023-06-20 22:08 ` [PATCH V9 0/6] Generate device tree node for pci devices Rob Herring
2023-06-21 20:29 ` Bjorn Helgaas
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