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From: WANG Xuerui <kernel@xen0n.name>
To: Huacai Chen <chenhuacai@kernel.org>
Cc: WANG Rui <wangrui@loongson.cn>, Xi Ruoyao <xry111@xry111.site>,
	loongarch@lists.linux.dev, linux-kbuild@vger.kernel.org,
	llvm@lists.linux.dev, linux-kernel@vger.kernel.org,
	WANG Xuerui <git@xen0n.name>
Subject: [PATCH 2/9] LoongArch: extable: Also recognize ABI names of registers
Date: Fri, 23 Jun 2023 21:43:44 +0800	[thread overview]
Message-ID: <20230623134351.1898379-3-kernel@xen0n.name> (raw)
In-Reply-To: <20230623134351.1898379-1-kernel@xen0n.name>

From: WANG Rui <wangrui@loongson.cn>

When the kernel is compiled with LLVM, the register names being handled
during exception fixup building are ABI names instead of bare $rNN
style. Add mapping for the ABI names for LLVM compatibility.

Signed-off-by: WANG Rui <wangrui@loongson.cn>
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/gpr-num.h | 30 ++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/loongarch/include/asm/gpr-num.h b/arch/loongarch/include/asm/gpr-num.h
index e0941af20c7e..996038da806d 100644
--- a/arch/loongarch/include/asm/gpr-num.h
+++ b/arch/loongarch/include/asm/gpr-num.h
@@ -9,6 +9,22 @@
 	.equ	.L__gpr_num_$r\num, \num
 	.endr
 
+	/* ABI names of registers */
+	.equ	.L__gpr_num_$ra, 1
+	.equ	.L__gpr_num_$tp, 2
+	.equ	.L__gpr_num_$sp, 3
+	.irp	num,0,1,2,3,4,5,6,7
+	.equ	.L__gpr_num_$a\num, 4 + \num
+	.endr
+	.irp	num,0,1,2,3,4,5,6,7,8
+	.equ	.L__gpr_num_$t\num, 12 + \num
+	.endr
+	.equ	.L__gpr_num_$s9, 22
+	.equ	.L__gpr_num_$fp, 22
+	.irp	num,0,1,2,3,4,5,6,7,8
+	.equ	.L__gpr_num_$s\num, 23 + \num
+	.endr
+
 #else /* __ASSEMBLY__ */
 
 #define __DEFINE_ASM_GPR_NUMS					\
@@ -16,6 +32,20 @@
 "	.irp	num,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \
 "	.equ	.L__gpr_num_$r\\num, \\num\n"			\
 "	.endr\n"						\
+"	.equ	.L__gpr_num_$ra, 1\n"				\
+"	.equ	.L__gpr_num_$tp, 2\n"				\
+"	.equ	.L__gpr_num_$sp, 3\n"				\
+"	.irp	num,0,1,2,3,4,5,6,7\n"				\
+"	.equ	.L__gpr_num_$a\\num, 4 + \\num\n"		\
+"	.endr\n"						\
+"	.irp	num,0,1,2,3,4,5,6,7,8\n"			\
+"	.equ	.L__gpr_num_$t\\num, 12 + \\num\n"		\
+"	.endr\n"						\
+"	.equ	.L__gpr_num_$s9, 22\n"				\
+"	.equ	.L__gpr_num_$fp, 22\n"				\
+"	.irp	num,0,1,2,3,4,5,6,7,8\n"			\
+"	.equ	.L__gpr_num_$s\\num, 23 + \\num\n"		\
+"	.endr\n"						\
 
 #endif /* __ASSEMBLY__ */
 
-- 
2.40.0


  parent reply	other threads:[~2023-06-23 13:44 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-23 13:43 [PATCH 0/9] LoongArch: Preliminary ClangBuiltLinux enablement WANG Xuerui
2023-06-23 13:43 ` [PATCH 1/9] LoongArch: Calculate various sizes in the linker script WANG Xuerui
2023-06-23 13:43 ` WANG Xuerui [this message]
2023-06-23 13:43 ` [PATCH 3/9] LoongArch: Prepare for assemblers with proper FCSR bank support WANG Xuerui
2023-06-23 16:00   ` Huacai Chen
2023-06-23 13:43 ` [PATCH 4/9] LoongArch: Make {read,write}_fcsr compatible with LLVM/Clang WANG Xuerui
2023-06-23 16:03   ` Huacai Chen
2023-06-23 13:43 ` [PATCH 5/9] LoongArch: Make the CPUCFG and CSR ops simple aliases of compiler built-ins WANG Xuerui
2023-06-23 13:43 ` [PATCH 6/9] LoongArch: Simplify the invtlb wrappers WANG Xuerui
2023-06-23 15:57   ` Huacai Chen
2023-06-23 13:43 ` [PATCH 7/9] LoongArch: Tweak CFLAGS for Clang compatibility WANG Xuerui
2023-06-23 16:39   ` Nick Desaulniers
2023-06-23 16:53     ` Xi Ruoyao
2023-06-23 17:05     ` WANG Xuerui
2023-06-23 17:00   ` Xi Ruoyao
2023-06-23 17:06     ` WANG Xuerui
2023-06-23 13:43 ` [PATCH 8/9] Makefile: Add loongarch target flag for Clang compilation WANG Xuerui
2023-06-23 15:58   ` Huacai Chen
2023-06-23 16:31   ` Nick Desaulniers
2023-06-23 13:43 ` [PATCH 9/9] LoongArch: Mark Clang LTO as working WANG Xuerui
2023-06-23 16:52   ` Nick Desaulniers

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