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From: WANG Xuerui <kernel@xen0n.name>
To: Huacai Chen <chenhuacai@kernel.org>
Cc: WANG Rui <wangrui@loongson.cn>, Xi Ruoyao <xry111@xry111.site>,
	loongarch@lists.linux.dev, linux-kbuild@vger.kernel.org,
	llvm@lists.linux.dev, linux-kernel@vger.kernel.org,
	WANG Xuerui <git@xen0n.name>
Subject: [PATCH 4/9] LoongArch: Make {read,write}_fcsr compatible with LLVM/Clang
Date: Fri, 23 Jun 2023 21:43:46 +0800	[thread overview]
Message-ID: <20230623134351.1898379-5-kernel@xen0n.name> (raw)
In-Reply-To: <20230623134351.1898379-1-kernel@xen0n.name>

From: WANG Xuerui <git@xen0n.name>

LLVM/Clang does not see FCSRs as GPRs, so make use of compiler
built-ins instead for better maintainability with less code.

The existing version cannot be wholly removed though, because the
built-ins, while available on GCC too, is predicated TARGET_HARD_FLOAT,
which means soft-float code cannot make use of them.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/loongarch.h | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index ac83e60c60d1..eedc313b5241 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1445,12 +1445,6 @@ __BUILD_CSR_OP(tlbidx)
 #define EXCCODE_INT_START	64
 #define EXCCODE_INT_END		(EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
 
-/* FPU register names */
-#define LOONGARCH_FCSR0	$r0
-#define LOONGARCH_FCSR1	$r1
-#define LOONGARCH_FCSR2	$r2
-#define LOONGARCH_FCSR3	$r3
-
 /* FPU Status Register Values */
 #define FPU_CSR_RSVD	0xe0e0fce0
 
@@ -1487,6 +1481,18 @@ __BUILD_CSR_OP(tlbidx)
 #define FPU_CSR_RU	0x200	/* towards +Infinity */
 #define FPU_CSR_RD	0x300	/* towards -Infinity */
 
+#ifdef CONFIG_CC_IS_CLANG
+#define LOONGARCH_FCSR0	0
+#define LOONGARCH_FCSR1	1
+#define LOONGARCH_FCSR2	2
+#define LOONGARCH_FCSR3	3
+#define read_fcsr(source)	__movfcsr2gr(source)
+#define write_fcsr(dest, val)	__movgr2fcsr(dest, val)
+#else /* CONFIG_CC_IS_CLANG */
+#define LOONGARCH_FCSR0	$r0
+#define LOONGARCH_FCSR1	$r1
+#define LOONGARCH_FCSR2	$r2
+#define LOONGARCH_FCSR3	$r3
 #define read_fcsr(source)	\
 ({	\
 	unsigned int __res;	\
@@ -1503,5 +1509,6 @@ do {	\
 	"	movgr2fcsr	"__stringify(dest)", %0	\n"	\
 	: : "r" (val));	\
 } while (0)
+#endif /* CONFIG_CC_IS_CLANG */
 
 #endif /* _ASM_LOONGARCH_H */
-- 
2.40.0


  parent reply	other threads:[~2023-06-23 13:44 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-23 13:43 [PATCH 0/9] LoongArch: Preliminary ClangBuiltLinux enablement WANG Xuerui
2023-06-23 13:43 ` [PATCH 1/9] LoongArch: Calculate various sizes in the linker script WANG Xuerui
2023-06-23 13:43 ` [PATCH 2/9] LoongArch: extable: Also recognize ABI names of registers WANG Xuerui
2023-06-23 13:43 ` [PATCH 3/9] LoongArch: Prepare for assemblers with proper FCSR bank support WANG Xuerui
2023-06-23 16:00   ` Huacai Chen
2023-06-23 13:43 ` WANG Xuerui [this message]
2023-06-23 16:03   ` [PATCH 4/9] LoongArch: Make {read,write}_fcsr compatible with LLVM/Clang Huacai Chen
2023-06-23 13:43 ` [PATCH 5/9] LoongArch: Make the CPUCFG and CSR ops simple aliases of compiler built-ins WANG Xuerui
2023-06-23 13:43 ` [PATCH 6/9] LoongArch: Simplify the invtlb wrappers WANG Xuerui
2023-06-23 15:57   ` Huacai Chen
2023-06-23 13:43 ` [PATCH 7/9] LoongArch: Tweak CFLAGS for Clang compatibility WANG Xuerui
2023-06-23 16:39   ` Nick Desaulniers
2023-06-23 16:53     ` Xi Ruoyao
2023-06-23 17:05     ` WANG Xuerui
2023-06-23 17:00   ` Xi Ruoyao
2023-06-23 17:06     ` WANG Xuerui
2023-06-23 13:43 ` [PATCH 8/9] Makefile: Add loongarch target flag for Clang compilation WANG Xuerui
2023-06-23 15:58   ` Huacai Chen
2023-06-23 16:31   ` Nick Desaulniers
2023-06-23 13:43 ` [PATCH 9/9] LoongArch: Mark Clang LTO as working WANG Xuerui
2023-06-23 16:52   ` Nick Desaulniers

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