From: Andrea Parri <parri.andrea@gmail.com>
To: mathieu.desnoyers@efficios.com, paulmck@kernel.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Andrea Parri <parri.andrea@gmail.com>
Subject: [RFC PATCH] membarrier: riscv: Provide core serializing command
Date: Thu, 3 Aug 2023 06:01:11 +0200 [thread overview]
Message-ID: <20230803040111.5101-1-parri.andrea@gmail.com> (raw)
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Suggested-by: Palmer Dabbelt <palmer@dabbelt.com>
---
For the MEMBARRIER maintainers: RISC-V does not have "core serializing
instructions", meaning that there is no occurence of such a term in the
RISC-V ISA. The discussion and git history about the SYNC_CORE command
suggested the implementation below: a FENCE.I instruction "synchronizes
the instruction and data streams" [1] on a CPU; in litmus parlance,
(single-hart test)
CPU0
UPDATE text ;
FENCE.I ;
EXECUTE text ; /* <-- will execute the updated/new text */
(message-passing test)
CPU0 CPU1
UPDATE text | IF (flag) { ;
WMB | FENCE.I ;
SET flag | EXECUTE text ; /* execute the new text */
| } ;
(and many others, including "maybe"s! ;-) )
How do these remarks resonate with the semantics of "a core serializing
instruction" (to be issued before returning to user-space)?
RISCV maintainers, I'm missing some paths to user-space? (besides xRET)
Andrea
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/zifencei.adoc
.../sched/membarrier-sync-core/arch-support.txt | 2 +-
arch/riscv/Kconfig | 2 ++
arch/riscv/include/asm/sync_core.h | 15 +++++++++++++++
3 files changed, 18 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/include/asm/sync_core.h
diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
index 23260ca449468..a17117d76e6d8 100644
--- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt
+++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
@@ -44,7 +44,7 @@
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
- | riscv: | TODO |
+ | riscv: | ok |
| s390: | ok |
| sh: | TODO |
| sparc: | TODO |
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4c07b9189c867..ed7ddaedc692e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -27,6 +27,7 @@ config RISCV
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_HAS_GIGANTIC_PAGE
select ARCH_HAS_KCOV
+ select ARCH_HAS_MEMBARRIER_SYNC_CORE
select ARCH_HAS_MMIOWB
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PMEM_API
@@ -35,6 +36,7 @@ config RISCV
select ARCH_HAS_SET_MEMORY if MMU
select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
+ select ARCH_HAS_SYNC_CORE_BEFORE_USERMODE
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UBSAN_SANITIZE_ALL
select ARCH_HAS_VDSO_DATA
diff --git a/arch/riscv/include/asm/sync_core.h b/arch/riscv/include/asm/sync_core.h
new file mode 100644
index 0000000000000..d3ec6ac47ac9b
--- /dev/null
+++ b/arch/riscv/include/asm/sync_core.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_SYNC_CORE_H
+#define _ASM_RISCV_SYNC_CORE_H
+
+/*
+ * Ensure that a core serializing instruction is issued before returning
+ * to user-mode. RISC-V implements return to user-space through an xRET
+ * instruction, which is not core serializing.
+ */
+static inline void sync_core_before_usermode(void)
+{
+ asm volatile ("fence.i" ::: "memory");
+}
+
+#endif /* _ASM_RISCV_SYNC_CORE_H */
--
2.34.1
next reply other threads:[~2023-08-03 4:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-03 4:01 Andrea Parri [this message]
2023-08-03 15:45 ` [RFC PATCH] membarrier: riscv: Provide core serializing command Andrea Parri
2023-08-03 20:28 ` Mathieu Desnoyers
2023-08-04 0:16 ` Andrea Parri
2023-08-04 14:20 ` Mathieu Desnoyers
2023-08-04 14:59 ` Andrea Parri
2023-08-04 18:05 ` Mathieu Desnoyers
2023-08-04 19:16 ` Andrea Parri
2023-08-04 20:06 ` Mathieu Desnoyers
2023-08-07 13:19 ` Andrea Parri
2023-10-13 17:29 ` Palmer Dabbelt
2023-10-13 18:49 ` Mathieu Desnoyers
2023-10-16 18:27 ` Robbin Ehn
2023-11-09 19:24 ` Andrea Parri
2023-11-10 6:33 ` [PATCH 1/2] locking: Introduce prepare_sync_core_cmd() kernel test robot
2023-11-23 1:07 ` [RFC PATCH] membarrier: riscv: Provide core serializing command Charlie Jenkins
2023-11-23 2:13 ` Mathieu Desnoyers
2023-11-27 10:44 ` Andrea Parri
2023-11-23 6:52 ` Robbin Ehn
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230803040111.5101-1-parri.andrea@gmail.com \
--to=parri.andrea@gmail.com \
--cc=aou@eecs.berkeley.edu \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mathieu.desnoyers@efficios.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=paulmck@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).