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From: Adam Skladowski <a39.skl@gmail.com>
To: unlisted-recipients:; (no To-header on input)
Cc: phone-devel@vger.kernel.org,
	~postmarketos/upstreaming@lists.sr.ht,
	Adam Skladowski <a39.skl@gmail.com>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	AngeloGioacchino Del Regno <kholk11@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 5/7] clk: qcom: hfpll: Add MSM8976 PLL data
Date: Sat, 12 Aug 2023 13:24:48 +0200	[thread overview]
Message-ID: <20230812112534.8610-6-a39.skl@gmail.com> (raw)
In-Reply-To: <20230812112534.8610-1-a39.skl@gmail.com>

Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
For simplicity only add second range as smaller frequencies can be obtained
via apcs divider or safe parent this also saves us
a hassle of reconfiguring VCO bit and config_val.
A72 and CCI cluster only use single frequency range with their
outputs/post_dividers/vco_bits being static.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 drivers/clk/qcom/hfpll.c | 54 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index 47325eb17f07..dac27e31ef60 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -32,8 +32,62 @@ static const struct hfpll_data hdata = {
 	.max_rate = 2900000000UL,
 };
 
+static const struct hfpll_data msm8976_a53 = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x341600,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.l_val = 0x35,
+	.user_val = 0x109,
+	.min_rate = 902400000UL,
+	.max_rate = 1478400000UL,
+};
+
+static const struct hfpll_data msm8976_a72 = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x4e0405d,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.l_val = 0x3e,
+	.user_val = 0x100109,
+	.min_rate = 940800000UL,
+	.max_rate = 2016000000UL,
+};
+
+static const struct hfpll_data msm8976_cci = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x141400,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.l_val = 0x20,
+	.user_val = 0x100109,
+	.min_rate = 556800000UL,
+	.max_rate = 902400000UL,
+};
+
 static const struct of_device_id qcom_hfpll_match_table[] = {
 	{ .compatible = "qcom,hfpll", .data = &hdata },
+	{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
+	{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
+	{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
-- 
2.41.0


  parent reply	other threads:[~2023-08-12 11:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-12 11:24 [PATCH v3 0/7] MSM8976 PLL,RPMPD and DTS changes Adam Skladowski
2023-08-12 11:24 ` [PATCH v3 1/7] drivers: genpd: qcom: rpmpd: Fix MSM8976 power domains setup Adam Skladowski
2023-09-13 19:05   ` Bjorn Andersson
2023-08-12 11:24 ` [PATCH v3 2/7] clk: qcom: clk-hfpll: Configure l_val in init when required Adam Skladowski
2023-08-12 11:24 ` [PATCH v3 3/7] clk: qcom: hfpll: Allow matching pdata Adam Skladowski
2023-08-12 11:48   ` Konrad Dybcio
2023-08-12 11:24 ` [PATCH v3 4/7] dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles Adam Skladowski
2023-08-12 11:24 ` Adam Skladowski [this message]
2023-08-12 15:48   ` [PATCH v3 5/7] clk: qcom: hfpll: Add MSM8976 PLL data Konrad Dybcio
2023-08-12 11:24 ` [PATCH v3 6/7] arm64: dts: qcom: msm8976: Split lpass region Adam Skladowski
2023-08-12 11:24 ` [PATCH v3 7/7] arm64: dts: qcom: msm8976: Fix ipc bit shifts Adam Skladowski
2023-09-14 16:04 ` (subset) [PATCH v3 0/7] MSM8976 PLL,RPMPD and DTS changes Bjorn Andersson
2023-09-20 18:15 ` Bjorn Andersson

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