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Tue, 12 Dec 2023 17:02:54 +0000 (UTC) Date: Tue, 12 Dec 2023 18:02:53 +0100 From: Borislav Petkov To: Michael Roth Cc: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, jroedel@suse.de, thomas.lendacky@amd.com, hpa@zytor.com, ardb@kernel.org, pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, jmattson@google.com, luto@kernel.org, dave.hansen@linux.intel.com, slp@redhat.com, pgonda@google.com, peterz@infradead.org, srinivas.pandruvada@linux.intel.com, rientjes@google.com, dovmurik@linux.ibm.com, tobin@ibm.com, vbabka@suse.cz, kirill@shutemov.name, ak@linux.intel.com, tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com, alpergun@google.com, jarkko@kernel.org, ashish.kalra@amd.com, nikunj.dadhania@amd.com, pankaj.gupta@amd.com, liam.merwick@oracle.com, zhi.a.wang@intel.com, Brijesh Singh Subject: Re: [PATCH v10 21/50] KVM: SEV: Add support to handle AP reset MSR protocol Message-ID: <20231212170253.GLZXiSPfJWXfuXzuM9@fat_crate.local> References: <20231016132819.1002933-1-michael.roth@amd.com> <20231016132819.1002933-22-michael.roth@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20231016132819.1002933-22-michael.roth@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 16, 2023 at 08:27:50AM -0500, Michael Roth wrote: > From: Tom Lendacky > > Add support for AP Reset Hold being invoked using the GHCB MSR protocol, > available in version 2 of the GHCB specification. > > Signed-off-by: Tom Lendacky > Signed-off-by: Brijesh Singh > Signed-off-by: Ashish Kalra > --- > arch/x86/include/asm/sev-common.h | 2 ++ > arch/x86/kvm/svm/sev.c | 56 ++++++++++++++++++++++++++----- > arch/x86/kvm/svm/svm.h | 1 + > 3 files changed, 51 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 93ec8c12c91d..57ced29264ce 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -56,6 +56,8 @@ > /* AP Reset Hold */ > #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 > #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) Align vertically pls. > /* GHCB GPA Register */ > #define GHCB_MSR_REG_GPA_REQ 0x012 > diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c > index 6ee925d66648..4f895a7201ed 100644 > --- a/arch/x86/kvm/svm/sev.c > +++ b/arch/x86/kvm/svm/sev.c > @@ -65,6 +65,10 @@ module_param_named(debug_swap, sev_es_debug_swap_enabled, bool, 0444); > #define sev_es_debug_swap_enabled false > #endif /* CONFIG_KVM_AMD_SEV */ > > +#define AP_RESET_HOLD_NONE 0 > +#define AP_RESET_HOLD_NAE_EVENT 1 > +#define AP_RESET_HOLD_MSR_PROTO 2 > + > static u8 sev_enc_bit; > static DECLARE_RWSEM(sev_deactivate_lock); > static DEFINE_MUTEX(sev_bitmap_lock); > @@ -2594,6 +2598,9 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) > > void sev_es_unmap_ghcb(struct vcpu_svm *svm) > { > + /* Clear any indication that the vCPU is in a type of AP Reset Hold */ > + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_NONE; > + > if (!svm->sev_es.ghcb) > return; > > @@ -2805,6 +2812,22 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) > GHCB_MSR_INFO_POS); > break; > } > + case GHCB_MSR_AP_RESET_HOLD_REQ: > + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_MSR_PROTO; > + ret = kvm_emulate_ap_reset_hold(&svm->vcpu); > + > + /* > + * Preset the result to a non-SIPI return and then only set > + * the result to non-zero when delivering a SIPI. > + */ > + set_ghcb_msr_bits(svm, 0, > + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, > + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); Yikes, those defines are a mouthful. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette