From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DE126088E for ; Tue, 23 Jan 2024 12:54:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706014444; cv=none; b=CrGHomN7RNbjxZP+jkli2bMyyABysT1uEwfNGcCSQLdt0l1ihHWcZMgGosSK/Kcw/0xxlux3gypa/ak2HjB7N1TtbYlwJ+tHzcZHxzQ0b/tCouiygJ6seD50cOgENZGzeNdQvsDyZcWN2XNHfX8431YDCwajPNOf/AaOMcnz3Lg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706014444; c=relaxed/simple; bh=IiVU/EQPGLAtjCv4Y2GFk70d/aytmYANUKUADaDyc3w=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=sWCNEC+6EvO96eMahJiOdz1OJuPZvfYChHGUyrtPdeEIyCZDxnSbbQ9oX8x5/KA4N2EvH5HPsF8JYx0fAcInAZIGvzg0CD4DljiJD/LmN2UC9+qPGz8vUgFNXPWo2YIN0Hw9dT4tsJU61lxLuxxMXsI1UTr4lWYlaqxksRn3yc0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HsZoHXy8; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tbSHBNLm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HsZoHXy8"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tbSHBNLm" Message-ID: <20240117115909.537148439@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706014441; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FJqT3mPgCqqamnmXXVMxEDykuKO5FlyIcFcBDU9yaR4=; b=HsZoHXy8+gRXUpUOH/XUP7HwSjmrpPS5d/+Kg8DwCvQZKiGhYiAPjs6grU2ThZbaDKEVo6 ZhYfHva3KHDLjem4JbfPVv4eO4Vd67OkaR16OJK5uRUFslYuH/pJLTlzpgPQG+08iUIZ5q vJpwqS8uV4XoYHO4zswYi8c6ukPDV9e0Hk1IlyAyUrSP3y/JYvVatdyvjGGRYQOkYNf4Ae 02FmC0gaSfN2nmKY1BIWzPaXeCaHsDXPTZn8dLlYgFIocI4TJYWjiDvrFUNS4MDkax2sGg I+Hs/8FV3THpoYMhuSiSAWCAfAVuvkeoTy42Scyf/DGLWjmIETQpfAGnhOwMcw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706014441; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FJqT3mPgCqqamnmXXVMxEDykuKO5FlyIcFcBDU9yaR4=; b=tbSHBNLmr0ByTI4PN3XIyfrGmgJGJ/lnJFqsBh2M5NYZzTUdI/wfz10ReiSqh533LX3R8Z lrl/msVk4iPWaEDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch v5 19/19] x86/apic/uv: Remove the private leaf 0xb parser References: <20240117115752.863482697@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Date: Tue, 23 Jan 2024 13:53:59 +0100 (CET) From: Thomas Gleixner The package shift has been already evaluated by the early CPU init. Put the mindless copy right next to the original leaf 0xb parser. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley --- arch/x86/include/asm/topology.h | 5 +++ arch/x86/kernel/apic/x2apic_uv_x.c | 52 ++++++------------------------------- 2 files changed, 14 insertions(+), 43 deletions(-) --- --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -126,6 +126,11 @@ static inline unsigned int topology_get_ return x86_topo_system.dom_size[dom]; } +static inline unsigned int topology_get_domain_shift(enum x86_topology_domains dom) +{ + return dom == TOPO_SMT_DOMAIN ? 0 : x86_topo_system.dom_shifts[dom - 1]; +} + extern const struct cpumask *cpu_coregroup_mask(int cpu); extern const struct cpumask *cpu_clustergroup_mask(int cpu); --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -241,54 +241,20 @@ static void __init uv_tsc_check_sync(voi is_uv(UV3) ? sname.s3.field : \ undef) -/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ - -#define SMT_LEVEL 0 /* Leaf 0xb SMT level */ -#define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ -#define SMT_TYPE 1 -#define CORE_TYPE 2 -#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) -#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) - -static void set_x2apic_bits(void) -{ - unsigned int eax, ebx, ecx, edx, sub_index; - unsigned int sid_shift; - - cpuid(0, &eax, &ebx, &ecx, &edx); - if (eax < 0xb) { - pr_info("UV: CPU does not have CPUID.11\n"); - return; - } - - cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { - pr_info("UV: CPUID.11 not implemented\n"); - return; - } - - sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); - sub_index = 1; - do { - cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); - if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { - sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); - break; - } - sub_index++; - } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); - - uv_cpuid.apicid_shift = 0; - uv_cpuid.apicid_mask = (~(-1 << sid_shift)); - uv_cpuid.socketid_shift = sid_shift; -} - static void __init early_get_apic_socketid_shift(void) { + unsigned int sid_shift = topology_get_domain_shift(TOPO_PKG_DOMAIN); + if (is_uv2_hub() || is_uv3_hub()) uvh_apicid.v = uv_early_read_mmr(UVH_APICID); - set_x2apic_bits(); + if (sid_shift) { + uv_cpuid.apicid_shift = 0; + uv_cpuid.apicid_mask = (~(-1 << sid_shift)); + uv_cpuid.socketid_shift = sid_shift; + } else { + pr_info("UV: CPU does not have valid CPUID.11\n"); + } pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);