From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C701536B1A; Tue, 13 Feb 2024 00:54:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707785700; cv=none; b=kdycZ/UUQf+y6hC9b+/96JdMrhIe7XfFlg8ciWWktki1purmepyxKzl3b8i4l2E7PKNP0sGcFkaV3ApTKg9lmHMG3OBMWV2KMGRwYOeEsaZjxsLZt/Rhx4+Nuc3thegFT92IFY++AhsQpGVy+mKN2HGmh4/REN6O9Ud+eod8Y5M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707785700; c=relaxed/simple; bh=CtxumE9xy8E75NV5EAWv+2S2i06ql2rIZ/FBzOnULFc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EHoXf+mvpQezWPTnP+Mk/bW/U9rXSZJS1Dv/Olor064WU2o/dJddVj4bQhFITpfmE7ZQ+UUEXVQYo3KxdaF5AHXHT5r8BXnomlGJ7+MwrnRxBanZXprEwYFmzyrU05a/8DGZtojWM0eS7uBP1lxgPl+EpHIhWHmcQ8QXYOzeMig= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CWHvJxFW; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CWHvJxFW" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41D0daLI010592; Tue, 13 Feb 2024 00:54:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=LylXK/jrWURWDhUw7tH5 hZ4ow+Xl5FX/mchvOMoIBg8=; b=CWHvJxFW3CG7Nq5F+/gjuZcjGEIUfigycJL6 gkpwBQCQS3C2GF/T4XrCwbCESRxKGmvkK3VeD188YiLkFsxECEy06e84AT+LBlEe ACaCpdRxOQDNXKMUYuPmVynXBvQrDFy2IvgenLm1veQFFHXLA5fIMFI2V+L9o8EJ j+Sohik82jvfleeRVUG3VwTsJ0wuhzXNjBGNNMEPYwqjOcDVr0gyA6wYScuqRcdk nTE4n1Vf3nqoyqoZypAHtzOjj9+BnTXs/nIVZjZVYwrW+JOjzqzIMjCxraTEpa68 OrKy6sgLkig1k/jNxwFeKp5jr+GZn4tfZqP4nHhCovxod4tOig== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w62kt4tyc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Feb 2024 00:54:37 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41D0saRO029979 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Feb 2024 00:54:36 GMT Received: from hu-wcheng-lv.qualcomm.com (10.49.16.6) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 12 Feb 2024 16:54:36 -0800 From: Wesley Cheng To: , , , , , , , , , , , , , , CC: , , , , , , , Wesley Cheng Subject: [PATCH v15 13/50] xhci: export XHCI IMOD setting helper for interrupters Date: Mon, 12 Feb 2024 16:53:45 -0800 Message-ID: <20240213005422.3121-14-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240213005422.3121-1-quic_wcheng@quicinc.com> References: <20240213005422.3121-1-quic_wcheng@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sBt5247R1FsB-HUETT6fcEINd9m01l8C X-Proofpoint-ORIG-GUID: sBt5247R1FsB-HUETT6fcEINd9m01l8C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_20,2024-02-12_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=642 spamscore=0 malwarescore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402130005 Utilize the xhci_set_interrupter_moderation() API to set the IMOD value for interrupters, so that secondary interrupts can also configure this parameter when clients request for it. Signed-off-by: Wesley Cheng --- drivers/usb/host/xhci.c | 3 ++- drivers/usb/host/xhci.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 834d8d160da4..d2ce1e1421e6 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -349,7 +349,7 @@ int xhci_disable_interrupter(struct xhci_interrupter *ir) EXPORT_SYMBOL_GPL(xhci_disable_interrupter); /* interrupt moderation interval imod_interval in nanoseconds */ -static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, +int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, u32 imod_interval) { u32 imod; @@ -364,6 +364,7 @@ static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, return 0; } +EXPORT_SYMBOL_GPL(xhci_set_interrupter_moderation); static void compliance_mode_recovery(struct timer_list *t) { diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index ad9d93c645ad..d88d2f67e3ed 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1874,6 +1874,8 @@ int xhci_alloc_tt_info(struct xhci_hcd *xhci, struct usb_tt *tt, gfp_t mem_flags); int xhci_enable_interrupter(struct xhci_interrupter *ir); int xhci_disable_interrupter(struct xhci_interrupter *ir); +int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, + u32 imod_interval); /* xHCI ring, segment, TRB, and TD functions */ dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);