From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E7A423747; Thu, 22 Feb 2024 08:41:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708591309; cv=none; b=bJjuTiG3U41UgF8ShTlxEcJxUym5yrDnJ+2x0BIt52cT1h3UHgHgyaj4HJmaHU2nypJLvFXX6rgJyULJ1KdNoPI8Lt8aUTo5xa4O+llrszBrU48MlVywJO47qiBySUPPtw7e6vRiMpu6qV8fu5aabzaR7jgHES0ELzQTwy+bEj4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708591309; c=relaxed/simple; bh=4l74eGatVrw0NbRx/OJFNCBiH2P+9Xv0zPZKmzV9+H8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MFTWJEbtjMNXAsudVXQmfD+qJaUXA1lChrb8d6+znkwCBK0byuJUajymOYy5Kd3A448laLBQ4QXX+TAJxl8Md8ETa+Hk0fK5LWvNJ0Z2R8ST6vy0GWH2tkUJ3aNkaeeLX6Rg27YiOwRAO4ocEhB/QkNh38dBJreZxbaDQFq0Tt4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 41M8eIvY074578; Thu, 22 Feb 2024 16:40:18 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 22 Feb 2024 16:40:14 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Date: Thu, 22 Feb 2024 16:39:41 +0800 Message-ID: <20240222083946.3977135-6-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240222083946.3977135-1-peterlin@andestech.com> References: <20240222083946.3977135-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 41M8eIvY074578 The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - No change Changes v4 -> v5: - Include Geert's Reviewed-by - Include Prabhakar's Reviewed/Tested-by Changes v5 -> v6: - No change Changes v6 -> v7: - No change Changes v7 -> v8: - No change Changes v8 -> v9: - No change --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index a92cfcfc021b..099f3df75b42 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -39,7 +39,7 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; -- 2.34.1