From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2F87C22EE0 for ; Mon, 26 Feb 2024 11:33:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708947237; cv=none; b=FMZKd0X9urnXchZrSd2EAUMi9wu/IVnKGjZh7e6EYYCfBklSg/1Z51nr//NeFt65vjyrCXgmd/SKXsBUgXMBRDK9sq5U/gSLB7by4FGMcwpjHv0vMP9zqSoy1sIX4iLSprHhHJQWQyBgji54kWO1SgU1liPTWibPL2Yz2eJoioc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708947237; c=relaxed/simple; bh=+nicV0g2b5jsmt8ZfpewvXZy/UwWJ4BnLx9od6RHkZg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MZu23AoYkaI6PMt6qR3oFjhP0LQmE31AGjGhPb/hOkUJjZwHQ3HeSbqfvjG1kJ4djgFEdVKDo3b5gkb5W9kkTGv7+Gq6Me/C1hXNPKnA5tvUp0x6wX/O1COO3t7tUaOFWgz4Y6YwlZGu7dOWSWNvF85OiJCZdCfokTaxWXMj4s4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D2CFDA7; Mon, 26 Feb 2024 03:34:34 -0800 (PST) Received: from e127643.broadband (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 302833F6C4; Mon, 26 Feb 2024 03:33:52 -0800 (PST) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, maz@kernel.org, suzuki.poulose@arm.com, acme@kernel.org, oliver.upton@linux.dev, broonie@kernel.org Cc: James Clark , James Morse , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Alexander Shishkin , Anshuman Khandual , Miguel Luis , Joey Gouly , Ard Biesheuvel , Quentin Perret , Javier Martinez Canillas , Mark Rutland , Arnd Bergmann , Vincent Donnefort , Ryan Roberts , Fuad Tabba , Jing Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v6 5/8] arm64: KVM: Add iflag for FEAT_TRF Date: Mon, 26 Feb 2024 11:30:33 +0000 Message-Id: <20240226113044.228403-6-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240226113044.228403-1-james.clark@arm.com> References: <20240226113044.228403-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add an extra iflag to signify if the TRFCR register is accessible. Because TRBE requires FEAT_TRF, DEBUG_STATE_SAVE_TRBE still has the same behavior even though it's only set when FEAT_TRF is present. The following holes are left in struct kvm_vcpu_arch, but there aren't enough other 8 bit fields to rearrange it to leave any hole smaller than 7 bytes: u8 cflags; /* 2292 1 */ /* XXX 1 byte hole, try to pack */ u16 iflags; /* 2294 2 */ u8 sflags; /* 2296 1 */ bool pause; /* 2297 1 */ /* XXX 6 bytes hole, try to pack */ Reviewed-by: Suzuki K Poulose Signed-off-by: James Clark --- arch/arm64/include/asm/kvm_host.h | 4 +++- arch/arm64/kvm/debug.c | 24 ++++++++++++++++++++---- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 21c57b812569..85b5477bd1b4 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -569,7 +569,7 @@ struct kvm_vcpu_arch { u8 cflags; /* Input flags to the hypervisor code, potentially cleared after use */ - u8 iflags; + u16 iflags; /* State flags for kernel bookkeeping, unused by the hypervisor code */ u8 sflags; @@ -779,6 +779,8 @@ struct kvm_vcpu_arch { #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) /* vcpu running in HYP context */ #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7)) +/* Save trace filter controls */ +#define DEBUG_STATE_SAVE_TRFCR __vcpu_single_flag(iflags, BIT(8)) /* SVE enabled for host EL0 */ #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index ce8886122ed3..49a13e72ddd2 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -332,14 +332,30 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); - /* Check if we have TRBE implemented and available at the host */ - if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && - !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) - vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + /* + * Set SAVE_TRFCR flag if FEAT_TRF (TraceFilt) exists. This flag + * signifies that the exclude_host/exclude_guest settings of any active + * host Perf session on a core running a VCPU can be written into + * TRFCR_EL1 on guest switch. + */ + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) { + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); + /* + * Check if we have TRBE implemented and available at the host. + * If it's in use at the time of guest switch then trace will + * need to be completely disabled. The architecture mandates + * FEAT_TRF with TRBE, so we only need to check for TRBE after + * TRF. + */ + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && + !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + } } void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) { vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_SPE); vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); } -- 2.34.1