From: Paolo Bonzini <pbonzini@redhat.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: seanjc@google.com, michael.roth@amd.com,
isaku.yamahata@intel.com, thomas.lendacky@amd.com
Subject: [PATCH 03/21] KVM: x86/mmu: Replace hardcoded value 0 for the initial value for SPTE
Date: Tue, 27 Feb 2024 18:20:42 -0500 [thread overview]
Message-ID: <20240227232100.478238-4-pbonzini@redhat.com> (raw)
In-Reply-To: <20240227232100.478238-1-pbonzini@redhat.com>
From: Sean Christopherson <seanjc@google.com>
The TDX support will need the "suppress #VE" bit (bit 63) set as the
initial value for SPTE. To reduce code change size, introduce a new macro
SHADOW_NONPRESENT_VALUE for the initial value for the shadow page table
entry (SPTE) and replace hard-coded value 0 for it. Initialize shadow page
tables with their value.
The plan is to unconditionally set the "suppress #VE" bit for both AMD and
Intel as: 1) AMD hardware uses the bit 63 as NX for present SPTE and
ignored for non-present SPTE; 2) for conventional VMX guests, KVM never
enables the "EPT-violation #VE" in VMCS control and "suppress #VE" bit is
ignored by hardware.
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Message-Id: <acdf09bf60cad12c495005bf3495c54f6b3069c9.1705965635.git.isaku.yamahata@intel.com>
[Remove unnecessary CONFIG_X86_64 check. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
arch/x86/kvm/mmu/mmu.c | 14 +++++++++-----
arch/x86/kvm/mmu/paging_tmpl.h | 2 +-
arch/x86/kvm/mmu/spte.h | 2 ++
arch/x86/kvm/mmu/tdp_mmu.c | 14 +++++++-------
4 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index e4cc7f764980..b5baf11359ad 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -567,9 +567,9 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
if (!is_shadow_present_pte(old_spte) ||
!spte_has_volatile_bits(old_spte))
- __update_clear_spte_fast(sptep, 0ull);
+ __update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
else
- old_spte = __update_clear_spte_slow(sptep, 0ull);
+ old_spte = __update_clear_spte_slow(sptep, SHADOW_NONPRESENT_VALUE);
if (!is_shadow_present_pte(old_spte))
return old_spte;
@@ -603,7 +603,7 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
*/
static void mmu_spte_clear_no_track(u64 *sptep)
{
- __update_clear_spte_fast(sptep, 0ull);
+ __update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
}
static u64 mmu_spte_get_lockless(u64 *sptep)
@@ -1950,7 +1950,8 @@ static bool kvm_sync_page_check(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
static int kvm_sync_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, int i)
{
- if (!sp->spt[i])
+ /* sp->spt[i] has initial value of shadow page table allocation */
+ if (sp->spt[i] == SHADOW_NONPRESENT_VALUE)
return 0;
return vcpu->arch.mmu->sync_spte(vcpu, sp, i);
@@ -6173,7 +6174,10 @@ int kvm_mmu_create(struct kvm_vcpu *vcpu)
vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
- vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
+ vcpu->arch.mmu_shadow_page_cache.init_value =
+ SHADOW_NONPRESENT_VALUE;
+ if (!vcpu->arch.mmu_shadow_page_cache.init_value)
+ vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
vcpu->arch.mmu = &vcpu->arch.root_mmu;
vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h
index 4d4e98fe4f35..bebd73cd61bb 100644
--- a/arch/x86/kvm/mmu/paging_tmpl.h
+++ b/arch/x86/kvm/mmu/paging_tmpl.h
@@ -911,7 +911,7 @@ static int FNAME(sync_spte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, int
gpa_t pte_gpa;
gfn_t gfn;
- if (WARN_ON_ONCE(!sp->spt[i]))
+ if (WARN_ON_ONCE(sp->spt[i] == SHADOW_NONPRESENT_VALUE))
return 0;
first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h
index a129951c9a88..4d1799ba2bf8 100644
--- a/arch/x86/kvm/mmu/spte.h
+++ b/arch/x86/kvm/mmu/spte.h
@@ -149,6 +149,8 @@ static_assert(MMIO_SPTE_GEN_LOW_BITS == 8 && MMIO_SPTE_GEN_HIGH_BITS == 11);
#define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0)
+#define SHADOW_NONPRESENT_VALUE 0ULL
+
extern u64 __read_mostly shadow_host_writable_mask;
extern u64 __read_mostly shadow_mmu_writable_mask;
extern u64 __read_mostly shadow_nx_mask;
diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index d078157e62aa..c8a4d92497b4 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -603,7 +603,7 @@ static inline int tdp_mmu_zap_spte_atomic(struct kvm *kvm,
* here since the SPTE is going from non-present to non-present. Use
* the raw write helper to avoid an unnecessary check on volatile bits.
*/
- __kvm_tdp_mmu_write_spte(iter->sptep, 0);
+ __kvm_tdp_mmu_write_spte(iter->sptep, SHADOW_NONPRESENT_VALUE);
return 0;
}
@@ -740,8 +740,8 @@ static void __tdp_mmu_zap_root(struct kvm *kvm, struct kvm_mmu_page *root,
continue;
if (!shared)
- tdp_mmu_iter_set_spte(kvm, &iter, 0);
- else if (tdp_mmu_set_spte_atomic(kvm, &iter, 0))
+ tdp_mmu_iter_set_spte(kvm, &iter, SHADOW_NONPRESENT_VALUE);
+ else if (tdp_mmu_set_spte_atomic(kvm, &iter, SHADOW_NONPRESENT_VALUE))
goto retry;
}
}
@@ -808,8 +808,8 @@ bool kvm_tdp_mmu_zap_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
if (WARN_ON_ONCE(!is_shadow_present_pte(old_spte)))
return false;
- tdp_mmu_set_spte(kvm, kvm_mmu_page_as_id(sp), sp->ptep, old_spte, 0,
- sp->gfn, sp->role.level + 1);
+ tdp_mmu_set_spte(kvm, kvm_mmu_page_as_id(sp), sp->ptep, old_spte,
+ SHADOW_NONPRESENT_VALUE, sp->gfn, sp->role.level + 1);
return true;
}
@@ -843,7 +843,7 @@ static bool tdp_mmu_zap_leafs(struct kvm *kvm, struct kvm_mmu_page *root,
!is_last_spte(iter.old_spte, iter.level))
continue;
- tdp_mmu_iter_set_spte(kvm, &iter, 0);
+ tdp_mmu_iter_set_spte(kvm, &iter, SHADOW_NONPRESENT_VALUE);
/*
* Zappings SPTEs in invalid roots doesn't require a TLB flush,
@@ -1276,7 +1276,7 @@ static bool set_spte_gfn(struct kvm *kvm, struct tdp_iter *iter,
* invariant that the PFN of a present * leaf SPTE can never change.
* See handle_changed_spte().
*/
- tdp_mmu_iter_set_spte(kvm, iter, 0);
+ tdp_mmu_iter_set_spte(kvm, iter, SHADOW_NONPRESENT_VALUE);
if (!pte_write(range->arg.pte)) {
new_spte = kvm_mmu_changed_pte_notifier_make_spte(iter->old_spte,
--
2.39.0
next prev parent reply other threads:[~2024-02-27 23:21 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-27 23:20 [PATCH 00/21] TDX/SNP part 1 of n, for 6.9 Paolo Bonzini
2024-02-27 23:20 ` [PATCH 01/21] KVM: x86: Split core of hypercall emulation to helper function Paolo Bonzini
2024-02-28 2:09 ` Xiaoyao Li
2024-03-05 6:24 ` Binbin Wu
2024-02-27 23:20 ` [PATCH 02/21] KVM: Allow page-sized MMU caches to be initialized with custom 64-bit values Paolo Bonzini
2024-02-29 13:46 ` Xiaoyao Li
2024-03-05 6:55 ` Binbin Wu
2024-03-26 15:56 ` Binbin Wu
2024-05-13 20:38 ` Isaku Yamahata
2024-05-13 20:51 ` Isaku Yamahata
2024-05-13 20:56 ` Sean Christopherson
2024-02-27 23:20 ` Paolo Bonzini [this message]
2024-02-29 13:50 ` [PATCH 03/21] KVM: x86/mmu: Replace hardcoded value 0 for the initial value for SPTE Xiaoyao Li
2024-03-05 7:09 ` Binbin Wu
2024-02-27 23:20 ` [PATCH 04/21] KVM: x86/mmu: Allow non-zero value for non-present SPTE and removed SPTE Paolo Bonzini
2024-02-29 7:00 ` Xu Yilun
2024-02-29 13:55 ` Xiaoyao Li
2024-03-11 23:26 ` Huang, Kai
2024-02-27 23:20 ` [PATCH 05/21] KVM: x86/mmu: Add Suppress VE bit to EPT shadow_mmio_mask/shadow_present_mask Paolo Bonzini
2024-03-01 7:26 ` Xiaoyao Li
2024-03-05 13:17 ` Binbin Wu
2024-02-27 23:20 ` [PATCH 06/21] KVM: x86/mmu: Track shadow MMIO value on a per-VM basis Paolo Bonzini
2024-03-01 7:44 ` Xiaoyao Li
2024-03-05 8:35 ` Binbin Wu
2024-03-12 1:21 ` Huang, Kai
2024-02-27 23:20 ` [PATCH 07/21] KVM: VMX: Introduce test mode related to EPT violation VE Paolo Bonzini
2024-02-28 1:56 ` Sean Christopherson
2024-03-12 1:35 ` Huang, Kai
2024-03-12 16:54 ` Sean Christopherson
2024-03-12 21:03 ` Huang, Kai
2024-02-27 23:20 ` [PATCH 08/21] KVM: VMX: Move out vmx_x86_ops to 'main.c' to dispatch VMX and TDX Paolo Bonzini
2024-02-27 23:20 ` [PATCH 09/21] KVM: VMX: Modify NMI and INTR handlers to take intr_info as function argument Paolo Bonzini
2024-03-04 8:09 ` Xiaoyao Li
2024-03-05 13:42 ` Binbin Wu
2024-03-12 1:43 ` Huang, Kai
2024-02-27 23:20 ` [PATCH 10/21] KVM: SEV: Use a VMSA physical address variable for populating VMCB Paolo Bonzini
2024-02-28 2:00 ` Sean Christopherson
2024-02-28 17:32 ` Paolo Bonzini
2024-02-29 16:02 ` Sean Christopherson
2024-02-27 23:20 ` [PATCH 11/21] KVM: x86/tdp_mmu: Init role member of struct kvm_mmu_page at allocation Paolo Bonzini
2024-03-03 4:47 ` Xu Yilun
2024-03-25 23:32 ` Edgecombe, Rick P
2024-02-27 23:20 ` [PATCH 12/21] KVM: x86/tdp_mmu: Sprinkle __must_check Paolo Bonzini
2024-03-04 8:29 ` Xiaoyao Li
2024-02-27 23:20 ` [PATCH 13/21] KVM: x86/mmu: Pass around full 64-bit error code for KVM page faults Paolo Bonzini
2024-03-04 8:56 ` Xiaoyao Li
2024-03-04 15:39 ` Sean Christopherson
2024-04-05 17:57 ` Paolo Bonzini
2024-02-27 23:20 ` [PATCH 14/21] KVM: x86/mmu: pass error code back to MMU when async pf is ready Paolo Bonzini
2024-02-28 2:03 ` Sean Christopherson
2024-02-28 13:13 ` Paolo Bonzini
2024-02-27 23:20 ` [PATCH 15/21] KVM: x86/mmu: Use PFERR_GUEST_ENC_MASK to indicate fault is private Paolo Bonzini
2024-02-27 23:20 ` [PATCH 16/21] KVM: guest_memfd: pass error up from filemap_grab_folio Paolo Bonzini
2024-03-03 14:41 ` Xu Yilun
2024-02-27 23:20 ` [PATCH 17/21] filemap: add FGP_CREAT_ONLY Paolo Bonzini
2024-02-28 2:14 ` Sean Christopherson
2024-02-28 2:17 ` Yosry Ahmed
2024-02-28 13:15 ` Matthew Wilcox
2024-02-28 13:28 ` Paolo Bonzini
2024-02-28 19:24 ` Matthew Wilcox
2024-02-28 20:17 ` Paolo Bonzini
2024-03-04 2:55 ` Xu Yilun
2024-02-27 23:20 ` [PATCH 18/21] KVM: x86: Add gmem hook for initializing memory Paolo Bonzini
2024-02-28 20:29 ` Isaku Yamahata
2024-02-27 23:20 ` [PATCH 19/21] KVM: guest_memfd: add API to undo kvm_gmem_get_uninit_pfn Paolo Bonzini
2024-03-04 4:44 ` Xu Yilun
2024-02-27 23:20 ` [PATCH 20/21] KVM: x86: Add gmem hook for invalidating memory Paolo Bonzini
2024-02-27 23:21 ` [PATCH 21/21] KVM: x86: Add gmem hook for determining max NPT mapping level Paolo Bonzini
2024-03-12 0:39 ` Binbin Wu
2024-03-12 0:48 ` Binbin Wu
2024-02-28 1:24 ` [PATCH 00/21] TDX/SNP part 1 of n, for 6.9 Sean Christopherson
2024-02-28 13:29 ` Paolo Bonzini
2024-02-28 16:39 ` Sean Christopherson
2024-02-28 17:20 ` Paolo Bonzini
2024-02-28 18:04 ` Sean Christopherson
2024-02-28 2:11 ` Sean Christopherson
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