From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Serge Semin <fancer.lancer@gmail.com>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Marek Vasut" <marek.vasut+renesas@gmail.com>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org,
mhi@lists.linux.dev, "Siddharth Vadapalli" <s-vadapalli@ti.com>,
"Frank Li" <Frank.Li@nxp.com>
Subject: Re: [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for HDMA platforms
Date: Mon, 18 Mar 2024 11:04:36 +0530 [thread overview]
Message-ID: <20240318053436.GE2748@thinkpad> (raw)
In-Reply-To: <kqztfm6ri54pkxcmsmngldmlf22mt2vn5cgxxfhjqxujx3qkq2@us6rc2sof7gk>
On Tue, Mar 12, 2024 at 12:17:48PM +0300, Serge Semin wrote:
> On Wed, Mar 06, 2024 at 03:51:58PM +0530, Manivannan Sadhasivam wrote:
> > In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way
> > the drivers can auto detect the number of read/write channels as like its
> > predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA
> > have to pass the channels count during probe.
> >
> > To accommodate that, let's skip the existing auto detection of channels
> > count procedure for HDMA based platforms. If the channels count passed by
> > the glue drivers were wrong in any form, then the existing sanity check
> > will catch it.
> >
> > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
>
> Please find a tiny nitpick further below.
>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++++++-----
> > 1 file changed, 10 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 3a26dfc5368f..599991b7ffb2 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -927,13 +927,18 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci)
> > {
> > u32 val;
> >
> > - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY)
> > - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> > - else
>
> > + /*
> > + * Autodetect the read/write channels count only for non-HDMA platforms.
> > + * HDMA platforms doesn't support autodetect, so the glue drivers should've
> > + * passed the valid count already. If not, the below sanity check will
> > + * catch it.
> > + */
>
> This is correct for the _native_ HDMA CSRs mapping. I suggest to emphasize
> that in the note above.
>
Ack.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-03-18 5:34 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 10:21 [PATCH v4 0/5] PCI: dwc: Add support for integrating HDMA with DWC EP driver Manivannan Sadhasivam
2024-03-06 10:21 ` [PATCH v4 1/5] PCI: dwc: Refactor dw_pcie_edma_find_chip() API Manivannan Sadhasivam
2024-03-08 11:41 ` Yoshihiro Shimoda
2024-03-12 9:04 ` Serge Semin
2024-03-18 5:29 ` Manivannan Sadhasivam
2024-03-06 10:21 ` [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for HDMA platforms Manivannan Sadhasivam
2024-03-08 11:42 ` Yoshihiro Shimoda
2024-03-12 9:17 ` Serge Semin
2024-03-18 5:34 ` Manivannan Sadhasivam [this message]
2024-03-06 10:21 ` [PATCH v4 3/5] PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers Manivannan Sadhasivam
2024-03-08 11:45 ` Yoshihiro Shimoda
2024-03-06 10:22 ` [PATCH v4 4/5] PCI: qcom-ep: Add HDMA support for SA8775P SoC Manivannan Sadhasivam
2024-03-06 10:22 ` [PATCH v4 5/5] PCI: epf-mhi: Enable HDMA " Manivannan Sadhasivam
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