From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757417Ab2BIIk3 (ORCPT ); Thu, 9 Feb 2012 03:40:29 -0500 Received: from mail.karo-electronics.de ([81.173.242.67]:51436 "EHLO mail.karo-electronics.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750929Ab2BIIk1 (ORCPT ); Thu, 9 Feb 2012 03:40:27 -0500 Message-ID: <20275.34409.978854.416870@ipc1.ka-ro> Date: Thu, 9 Feb 2012 09:40:09 +0100 From: =?utf-8?Q?Lothar_Wa=C3=9Fmann?= To: Thomas Gleixner Cc: linux-kernel@vger.kernel.org, Lars-Peter Clausen , Yong Zhang , linux-arm-kernel@lists.infradead.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [PATCH] genirq: Fix race condition in ONESHOT irq handler In-Reply-To: References: <4F31220A.2050708@metafoo.de> <1328621921-17404-1-git-send-email-LW@KARO-electronics.de> <20274.4237.63380.338503@ipc1.ka-ro> X-Mailer: VM 8.1.0 under 23.2.1 (i486-pc-linux-gnu) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Thomas Gleixner writes: > On Wed, 8 Feb 2012, Lothar Waßmann wrote: > > > > The problem arises also with interrupt controllers that latch a level > > > > triggered IRQ until it is acknowledged (like the i.MX28 does). > > > > In this case the IRQ status bit will remain asserted after the > > > > soft-irq finishes and retrigger the interrupt while the interrupt line > > > > is already deasserted. > > > > > > This does not make sense. We acknowledge interrupts via mask_ack_irq() > > > right on entry of handle_level_irq(). So either the interrupt > > > > > That's right. But at that point the IRQ line is still asserted and > > since it is a level IRQ this will not actually clear the interrupt > > status bit. Normally the IRQ status bit would self-clear when the IRQ > > line is being deasserted (in this case by removing the finger from the > > touch panel). But the i.MX28 leaves the IRQ status bit set and it > > takes another write to the IRQ status register to remove the bogus IRQ > > status. > > So the question is whether the imx irq chip implementation should > write to the status register on unmask for level type irqs to avoid > spurious interrupts being generated in the first place. This is not > only an optimization for threaded interrupts, afaict this spurious > effect should happen with non threaded interrupts as well. > > Did my patch work for you ? > Sorry, I couldn't test it earlier. Yes, it works. Lothar Waßmann -- ___________________________________________________________ Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10 Geschäftsführer: Matthias Kaussen Handelsregistereintrag: Amtsgericht Aachen, HRB 4996 www.karo-electronics.de | info@karo-electronics.de ___________________________________________________________