From: Randy Dunlap <rdunlap@infradead.org>
To: Ramakrishna Saripalli <rsaripal@amd.com>,
linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
Jonathan Corbet <corbet@lwn.net>
Cc: bsd@redhat.com
Subject: Re: [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Forwarding
Date: Mon, 17 May 2021 19:55:53 -0700 [thread overview]
Message-ID: <20c6fa3d-949d-156a-6d74-89829e3bffdf@infradead.org> (raw)
In-Reply-To: <20210517220059.6452-2-rsaripal@amd.com>
Hi again,
On 5/17/21 3:00 PM, Ramakrishna Saripalli wrote:
> From: Ramakrishna Saripalli <rk.saripalli@amd.com>
>
> Certain AMD processors feature a new technology called Predictive Store
> Forwarding (PSF).
>
> PSF is a micro-architectural optimization designed to improve the
> performance of code execution by predicting dependencies between
> loads and stores.
>
> Incorrect PSF predictions can occur due to two reasons.
>
...
>
> Kernel parameter predictive_store_fwd_disable has the following values
>
> - on. Disable PSF on all CPUs.
>
> - off. Enable PSF on all CPUs.
> This is also the default setting.
>
> Signed-off-by: Ramakrishna Saripalli<rk.saripalli@amd.com>
> ---
> .../admin-guide/kernel-parameters.txt | 5 +
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/include/asm/msr-index.h | 2 +
> arch/x86/include/asm/nospec-branch.h | 6 ++
> arch/x86/kernel/cpu/bugs.c | 94 +++++++++++++++++++
> 5 files changed, 108 insertions(+)
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 04545725f187..a5f694dccb24 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -3940,6 +3940,11 @@
> Format: {"off"}
> Disable Hardware Transactional Memory
>
> + predictive_store_fwd_disable= [X86] This option controls PSF.
> + off - Turns on PSF.
> + on - Turns off PSF.
> + default : off.
and as I did earlier, I still object to "off" meaning PSF is on
and "on" meaning that PSF is off.
It's not at all user friendly.
If it's done this way because that's how the h/w bit is defined/used,
that's not a good excuse IMHO.
Hm, it sorta seems to be a common "theme" when dealing with mitigations.
And too late to fix that.
I look forward to h/w that doesn't need mitigations. ;)
--
~Randy
next prev parent reply other threads:[~2021-05-18 2:56 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 22:00 [v6 0/1] Introduce support for PSF control Ramakrishna Saripalli
2021-05-17 22:00 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Forwarding Ramakrishna Saripalli
2021-05-18 2:55 ` Randy Dunlap [this message]
2021-05-18 12:27 ` Saripalli, RK
2021-05-18 20:35 ` Pawan Gupta
2021-05-19 5:38 ` Pawan Gupta
2021-05-19 13:19 ` Saripalli, RK
2021-05-19 5:50 ` Pawan Gupta
2021-09-01 20:20 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Babu Moger
2021-09-01 20:30 ` Babu Moger
2021-09-01 20:35 ` Babu Moger
2021-09-02 17:35 ` Pawan Gupta
2021-08-12 23:44 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Forwarding Josh Poimboeuf
2021-09-02 18:16 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Babu Moger
2021-09-03 0:07 ` Josh Poimboeuf
[not found] ` <dca004cf-bacc-1a1f-56d6-c06e8bec167a@amd.com>
2021-09-04 17:23 ` Josh Poimboeuf
2021-09-07 23:15 ` Babu Moger
2021-09-08 18:20 ` Josh Poimboeuf
2021-09-10 16:08 ` Babu Moger
2021-09-09 16:20 ` Bandan Das
2021-06-17 20:47 ` [v6 0/1] Introduce support for PSF control Saripalli, RK
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