From: "Arnd Bergmann" <arnd@arndb.de>
To: Prabhakar <prabhakar.csengg@gmail.com>,
"Conor.Dooley" <conor.dooley@microchip.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
guoren <guoren@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Samuel Holland" <samuel@sholland.org>,
linux-riscv@lists.infradead.org,
"Christoph Hellwig" <hch@infradead.org>
Cc: "Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"Biju Das" <biju.das.jz@bp.renesas.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v9 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
Date: Wed, 14 Jun 2023 15:10:45 +0200 [thread overview]
Message-ID: <20d4d296-14d7-467d-826c-b5c9cdf4599a@app.fastmail.com> (raw)
In-Reply-To: <20230614104759.228372-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Wed, Jun 14, 2023, at 12:47, Prabhakar wrote:
> +static void ax45mp_dma_cache_inv(phys_addr_t paddr, unsigned long size)
> +{
> + unsigned long start = (unsigned long)phys_to_virt(paddr);
> + char cache_buf[2][AX45MP_CACHE_LINE_SIZE];
> + unsigned long end = start + size;
> + unsigned long old_start = start;
> + unsigned long old_end = end;
> + unsigned long line_size;
> + unsigned long flags;
> +
> + if (unlikely(start == end))
> + return;
> +
> + line_size = ax45mp_priv.ax45mp_cache_line_size;
> +
> + memset(&cache_buf, 0x0, sizeof(cache_buf));
> + start = start & (~(line_size - 1));
> + end = ((end + line_size - 1) & (~(line_size - 1)));
> +
> + local_irq_save(flags);
> + if (unlikely(start != old_start))
> + memcpy(&cache_buf[0][0], (void *)start, line_size);
> +
> + if (unlikely(end != old_end))
> + memcpy(&cache_buf[1][0], (void *)(old_end & (~(line_size - 1))),
> line_size);
> +
> + ax45mp_cpu_dcache_inval_range(start, end, line_size);
> +
> + if (unlikely(start != old_start))
> + memcpy((void *)start, &cache_buf[0][0], (old_start & (line_size -
> 1)));
> +
> + local_irq_restore(flags);
> +}
I'm not quite sure what this does, maybe some comments would help.
This looks like a novel method of preserving partial cache lines
at the beginning (but not the end?) of an unaligned area.
As far as I can tell, most dma_mapping implementations don't
even try to do that at all, but the ones that do take a different
approach by calling _wback_inv() on partial cache lines instead
of calling _inv().
I'd say this does not belong into the low-level operations
here, especially since the ZICBOM variant doesn't do this either.
Arnd
next prev parent reply other threads:[~2023-06-14 13:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 10:47 [PATCH v9 0/6] Add non-coherent DMA support for AX45MP Prabhakar
2023-06-14 10:47 ` [PATCH v9 1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-06-14 10:47 ` [PATCH v9 2/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-06-14 10:47 ` [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support Prabhakar
2023-06-14 12:35 ` Arnd Bergmann
2023-06-15 6:00 ` Christoph Hellwig
2023-06-16 12:13 ` Lad, Prabhakar
2023-06-14 12:53 ` Geert Uytterhoeven
2023-06-14 16:43 ` Conor Dooley
2023-06-16 12:23 ` Lad, Prabhakar
2023-06-14 10:47 ` [PATCH v9 4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-06-14 10:47 ` [PATCH v9 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-06-14 13:10 ` Arnd Bergmann [this message]
2023-06-28 12:57 ` Lad, Prabhakar
2023-06-14 10:47 ` [PATCH v9 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-06-14 16:58 ` [PATCH v9 0/6] Add non-coherent DMA support for AX45MP Conor Dooley
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