From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3991C433E0 for ; Mon, 4 Jan 2021 03:45:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86F202137B for ; Mon, 4 Jan 2021 03:45:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727053AbhADDpG (ORCPT ); Sun, 3 Jan 2021 22:45:06 -0500 Received: from foss.arm.com ([217.140.110.172]:50586 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725840AbhADDpG (ORCPT ); Sun, 3 Jan 2021 22:45:06 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 320B9101E; Sun, 3 Jan 2021 19:44:20 -0800 (PST) Received: from [192.168.0.130] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F1D323F66E; Sun, 3 Jan 2021 19:44:16 -0800 (PST) Subject: Re: [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE To: Rob Herring Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Mathieu Poirier , Suzuki K Poulose , Mike Leach , Linu Cherian , devicetree@vger.kernel.org References: <1608717823-18387-1-git-send-email-anshuman.khandual@arm.com> <1608717823-18387-12-git-send-email-anshuman.khandual@arm.com> <20210103170540.GA4055084@robh.at.kernel.org> From: Anshuman Khandual Message-ID: <21536a1c-0878-a390-aff3-fc2300be6941@arm.com> Date: Mon, 4 Jan 2021 09:14:24 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210103170540.GA4055084@robh.at.kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/3/21 10:35 PM, Rob Herring wrote: > On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote: >> This patch documents the device tree binding in use for Arm TRBE. >> >> Cc: devicetree@vger.kernel.org >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Cc: Suzuki K Poulose >> Signed-off-by: Anshuman Khandual >> --- >> Changes in V1: >> >> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension' >> >> Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt >> new file mode 100644 >> index 0000000..001945d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/trbe.txt >> @@ -0,0 +1,20 @@ >> +* Trace Buffer Extension (TRBE) >> + >> +Trace Buffer Extension (TRBE) is used for collecting trace data generated >> +from a corresponding trace unit (ETE) using an in memory trace buffer. >> + >> +** TRBE Required properties: >> + >> +- compatible : should be one of: >> + "arm,trace-buffer-extension" >> + >> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where >> + TRBE is only supported on a subset of the CPUs, please consult >> + the arm,gic-v3 binding for details on describing a PPI partition. >> + >> +** Example: >> + >> +trbe { >> + compatible = "arm,trace-buffer-extension"; >> + interrupts = ; > > If only an interrupt, then could just be part of ETE? If not, how is > this hardware block accessed? An interrupt alone is not enough unless > there's some architected way to access. TRBE hardware block is accessed via respective new system registers but the PPI number where the IRQ will be triggered for various buffer events, would depend on the platform as defined in the SBSA. TRBE would need a ETE to work but the reverse is not true. ETE might just be present without a corresponding TRBE and can work with traditional sinks. Hence just wondering whether it would be prudent to add the TRBE interrupt number as part of the ETE DT specification.