From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751492AbeAVTBJ (ORCPT ); Mon, 22 Jan 2018 14:01:09 -0500 Received: from edison.jonmasters.org ([173.255.233.168]:55870 "EHLO edison.jonmasters.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751170AbeAVTBH (ORCPT ); Mon, 22 Jan 2018 14:01:07 -0500 To: Will Deacon , Jayachandran C References: <20180118135354.GB20783@arm.com> <1516364568-95577-1-git-send-email-jnair@caviumnetworks.com> <20180122113311.GB15456@arm.com> Cc: marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org From: Jon Masters Organization: World Organi{s,z}ation Of Broken Dreams Message-ID: <2232c6e4-c55f-4e57-c58f-2bfc02b2fac2@jonmasters.org> Date: Mon, 22 Jan 2018 14:00:59 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.0 MIME-Version: 1.0 In-Reply-To: <20180122113311.GB15456@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 68.173.157.109 X-SA-Exim-Mail-From: jcm@jonmasters.org Subject: Re: [PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2 X-SA-Exim-Version: 4.2.1 (built Sun, 08 Nov 2009 07:31:22 +0000) X-SA-Exim-Scanned: Yes (on edison.jonmasters.org) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/22/2018 06:33 AM, Will Deacon wrote: > On Fri, Jan 19, 2018 at 04:22:47AM -0800, Jayachandran C wrote: >> Use PSCI based mitigation for speculative execution attacks targeting >> the branch predictor. We use the same mechanism as the one used for >> Cortex-A CPUs, we expect the PSCI version call to have a side effect >> of clearing the BTBs. >> >> Signed-off-by: Jayachandran C >> --- >> arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index 70e5f18..45ff9a2 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -338,6 +338,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT, >> MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), >> }, >> + { >> + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, >> + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), >> + .enable = enable_psci_bp_hardening, >> + }, >> + { >> + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, >> + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), >> + .enable = enable_psci_bp_hardening, >> + }, >> #endif > > Thanks. > > Acked-by: Will Deacon Thanks. I have separately asked for a specification tweak to allow us to discover whether firmware has been augmented to provide the necessary support that we need. That applies beyond Cavium. (for now in RHEL, we've asked the vendors to give us a temporary patch that we can match DMI or other data later in boot and warn users on) Jon.