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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id cn19-20020a0564020cb300b0043bdc47803csm8142604edb.30.2022.08.16.02.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 02:25:54 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Samuel Holland , Chen-Yu Tsai , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, Krzysztof Kozlowski , Heiko =?ISO-8859-1?Q?St=FCbner?= Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Date: Tue, 16 Aug 2022 11:25:53 +0200 Message-ID: <2249129.ElGaqSPkdT@jernej-laptop> In-Reply-To: <3881930.ZaRXLXkqSa@diego> References: <20220815050815.22340-1-samuel@sholland.org> <5593349.DvuYhMxLoT@jernej-laptop> <3881930.ZaRXLXkqSa@diego> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko St=C3=BCbner napisal(a= ): > Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej =C5=A0krabec: > > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski=20 napisal(a): > > > On 15/08/2022 08:08, Samuel Holland wrote: > > > > + > > > > + de: display-engine { > > > > + compatible =3D "allwinner,sun20i-d1-display-engine"; > > > > + allwinner,pipelines =3D <&mixer0>, <&mixer1>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + osc24M: osc24M-clk { > > >=20 > > > lowercase > > >=20 > > > > + compatible =3D "fixed-clock"; > > > > + clock-frequency =3D <24000000>; > > >=20 > > > This is a property of the board, not SoC. > >=20 > > SoC needs 24 MHz oscillator for correct operation, so each and every bo= ard > > has it. Having it here simplifies board DT files. >=20 > I guess the oscillator is a separate component on each board, right? Correct. > And DT obvious is meant to describe the hardware - independently from > implementation-specific choices. There is no choice in this case. 24 MHz crystal has to be present. =46WIW, including crystal node in SoC specific DTSI is already common patte= rn in=20 Allwinner ARM SoC DTSI files. >=20 > Starting to discuss which exceptions to allow then might lead to even more > exceptions. >=20 > Also having to look for a board-component in the soc dtsi also is surpris= ing > if one gets to the party later on :-) . As I said, if one is accustomed to Allwinner ARM DT development, it would b= e=20 more surprising to include 24 MHz crystal node in each and every board DT. Best regards, Jernej