From: Jiancheng Xue <xuejiancheng@hisilicon.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: <mturquette@baylibre.com>, <sboyd@codeaurora.org>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<xuwei5@hisilicon.com>, <arnd@arndb.de>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<yanhaifeng@hisilicon.com>, <wenpan@hisilicon.com>,
<howell.yang@hisilicon.com>, <hermit.wangheming@hisilicon.com>,
<elder@linaro.org>, <bin.chen@linaro.org>
Subject: Re: [PATCH] reset: hisilicon: add a polarity cell for reset line specifier
Date: Fri, 25 Nov 2016 11:45:08 +0800 [thread overview]
Message-ID: <2281ff0d-2883-a78c-6106-f913da24581f@hisilicon.com> (raw)
In-Reply-To: <03bb74da-6b24-ee4c-307d-3b3f10ac2f7a@hisilicon.com>
On 2016/11/21 10:58, Jiancheng Xue wrote:
> Hi Philipp,
>
>> On 2016/11/15 18:43, Philipp Zabel wrote:
>>> Hi Jiancheng,
>>>
>>> Am Dienstag, den 15.11.2016, 15:09 +0800 schrieb Jiancheng Xue:
>>>> Add a polarity cell for reset line specifier. If the reset line
>>>> is asserted when the register bit is 1, the polarity is
>>>> normal. Otherwise, it is inverted.
>>>>
>>>> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
>>>> ---
>> Thank you very much for replying so soon.
>>
>> Please allow me to decribe the reason why this patch exists first.
>> All bits in the reset controller were designed to be active-high.
>> But in a recent chip only one bit was implemented to be active-low :(
>>
>>>> .../devicetree/bindings/clock/hisi-crg.txt | 11 ++++---
>>>> arch/arm/boot/dts/hi3519.dtsi | 2 +-
>>>> drivers/clk/hisilicon/reset.c | 36 ++++++++++++++++------
>>>> 3 files changed, 33 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt
>>>> index e3919b6..fcbb4f3 100644
>>>> --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt
>>>> +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt
>>>> @@ -25,19 +25,20 @@ to specify the clock which they consume.
>>>>
>>>> All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
>>>>
>>>> -- #reset-cells: should be 2.
>>>> +- #reset-cells: should be 3.
>>>>
>>>> A reset signal can be controlled by writing a bit register in the CRG module.
>>>> -The reset specifier consists of two cells. The first cell represents the
>>>> +The reset specifier consists of three cells. The first cell represents the
>>>> register offset relative to the base address. The second cell represents the
>>>> -bit index in the register.
>>>> +bit index in the register. The third cell represents the polarity of the reset
>>>> +line (0 for normal, 1 for inverted).
>>>
> #reset-cells: Should be 2 if compatilbe string is "hisilicon,hi3519-crg". Should be 3 otherwise.
> A reset signal can be controlled by writing a bit register in the CRG module.
> The reset specifier consists of two or three cells. The first cell represents the
> register offset relative to the base address. The second cell represents the
> bit index in the register.The third cell represents the polarity of the reset
> line (0 for active-high, 1 for active-low).
>
> If I change the binding like this, can it be accepted?
>
Hi Philipp,
Could you give me more suggestions about this? If you really don't like changing the
reset-cells like this, I can modify the patch according to your suggestions.
Thank you.
Regards,
Jiancheng
next prev parent reply other threads:[~2016-11-25 3:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-15 7:09 [PATCH] reset: hisilicon: add a polarity cell for reset line specifier Jiancheng Xue
2016-11-15 10:43 ` Philipp Zabel
2016-11-16 3:17 ` Jiancheng Xue
2016-11-21 2:58 ` Jiancheng Xue
2016-11-25 3:45 ` Jiancheng Xue [this message]
2016-11-25 8:05 ` Jiancheng Xue
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2281ff0d-2883-a78c-6106-f913da24581f@hisilicon.com \
--to=xuejiancheng@hisilicon.com \
--cc=arnd@arndb.de \
--cc=bin.chen@linaro.org \
--cc=elder@linaro.org \
--cc=hermit.wangheming@hisilicon.com \
--cc=howell.yang@hisilicon.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=sboyd@codeaurora.org \
--cc=wenpan@hisilicon.com \
--cc=xuwei5@hisilicon.com \
--cc=yanhaifeng@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).