From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82210ECDE44 for ; Fri, 26 Oct 2018 18:25:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 44E7C2085B for ; Fri, 26 Oct 2018 18:25:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44E7C2085B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728038AbeJ0DDP (ORCPT ); Fri, 26 Oct 2018 23:03:15 -0400 Received: from mga09.intel.com ([134.134.136.24]:3611 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727685AbeJ0DDO (ORCPT ); Fri, 26 Oct 2018 23:03:14 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2018 11:25:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,428,1534834800"; d="scan'208";a="85867440" Received: from schen9-desk.jf.intel.com (HELO [10.54.74.144]) ([10.54.74.144]) by orsmga006.jf.intel.com with ESMTP; 26 Oct 2018 11:25:10 -0700 Subject: Re: [Patch v3 09/13] x86/speculation: Reorganize SPEC_CTRL MSR update To: Waiman Long , Jiri Kosina , Thomas Gleixner Cc: Tom Lendacky , Ingo Molnar , Peter Zijlstra , Josh Poimboeuf , Andrea Arcangeli , David Woodhouse , Andi Kleen , Dave Hansen , Casey Schaufler , Asit Mallick , Arjan van de Ven , Jon Masters , linux-kernel@vger.kernel.org, x86@kernel.org References: <23d8ffaac99be49aa163eb16dd131399141fc432.1539798901.git.tim.c.chen@linux.intel.com> <63856b8d-0b53-7103-db7e-315330e2ee48@gmail.com> From: Tim Chen Openpgp: preference=signencrypt Autocrypt: addr=tim.c.chen@linux.intel.com; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: <63856b8d-0b53-7103-db7e-315330e2ee48@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/26/2018 10:21 AM, Waiman Long wrote: > On 10/17/2018 01:59 PM, Tim Chen wrote: >> Reorganize the spculation control MSR update code. Currently it is limited >> to only dynamic update of the Speculative Store Bypass Disable bit. >> This patch consolidates the logic to check for AMD CPUs that may or may >> not use this MSR to control SSBD. This prepares us to add logic to update >> other bits in the SPEC_CTRL MSR cleanly. >> >> Originally-by: Thomas Lendacky >> Signed-off-by: Tim Chen >> --- >> arch/x86/kernel/process.c | 39 +++++++++++++++++++++++++++++---------- >> 1 file changed, 29 insertions(+), 10 deletions(-) >> >> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c >> index 8aa4960..789f1bada 100644 >> --- a/arch/x86/kernel/process.c >> +++ b/arch/x86/kernel/process.c >> @@ -397,25 +397,45 @@ static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) >> >> static __always_inline void spec_ctrl_update_msr(unsigned long tifn) >> { >> - u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn); >> + u64 msr = x86_spec_ctrl_base; >> + >> + /* >> + * If X86_FEATURE_SSBD is not set, the SSBD >> + * bit is not to be touched. >> + */ >> + if (static_cpu_has(X86_FEATURE_SSBD)) >> + msr |= ssbd_tif_to_spec_ctrl(tifn); >> >> wrmsrl(MSR_IA32_SPEC_CTRL, msr); >> } >> >> -static __always_inline void __speculation_ctrl_update(unsigned long tifn) >> +static __always_inline void __speculation_ctrl_update(unsigned long tifp, >> + unsigned long tifn) > > I think it will be more intuitive to pass in (tifp ^ tifn) as bitmask of > changed TIF bits than tifp alone as you are only interested in the > changed bits anyway. I will need to then pass the bitmask plus tifn. I still need to pass two parameters and it is a bit more work for the caller to generate the bit mask. It is not obvious to me that it is better. Please also document the input parameters as it is > hard to know what they are by reading the function alone. Sure. > > Cheers, > Longman >> { >> - if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) >> - amd_set_ssb_virt_state(tifn); >> - else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) >> - amd_set_core_ssb_state(tifn); >> - else >> + bool updmsr = false; >> + >> + /* Check for AMD cpu to see if it uses SPEC_CTRL MSR for SSBD */ >> + if ((tifp ^ tifn) & _TIF_SSBD) { >> + if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) >> + amd_set_ssb_virt_state(tifn); >> + else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) >> + amd_set_core_ssb_state(tifn); >> + else if (static_cpu_has(X86_FEATURE_SSBD)) >> + updmsr = true; >> + } >> + >> + if (updmsr) >> spec_ctrl_update_msr(tifn); >> } >> >> void speculation_ctrl_update(unsigned long tif) >> { >> + /* >> + * On this path we're forcing the update, so use ~tif as the >> + * previous flags. >> + */ >> preempt_disable(); >> - __speculation_ctrl_update(tif); >> + __speculation_ctrl_update(~tif, tif); >> preempt_enable(); >> } >> >> @@ -451,8 +471,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, >> if ((tifp ^ tifn) & _TIF_NOCPUID) >> set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); >> >> - if ((tifp ^ tifn) & _TIF_SSBD) >> - __speculation_ctrl_update(tifn); >> + __speculation_ctrl_update(tifp, tifn); >> } >> >> /* > >