From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932742AbcKHQVH (ORCPT ); Tue, 8 Nov 2016 11:21:07 -0500 Received: from mout.kundenserver.de ([212.227.17.10]:49740 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752979AbcKHQVC (ORCPT ); Tue, 8 Nov 2016 11:21:02 -0500 From: Arnd Bergmann To: Mark Rutland Cc: "zhichang.yuan" , catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, bhelgaas@google.com, olof@lixom.net, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, linuxarm@huawei.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, minyard@acm.org, benh@kernel.crashing.org, liviu.dudau@arm.com, zourongrong@gmail.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, zhichang.yuan02@gmail.com, kantyzc@163.com, xuwei5@hisilicon.com, marc.zyngier@arm.com Subject: Re: [PATCH V5 2/3] ARM64 LPC: Add missing range exception for special ISA Date: Tue, 08 Nov 2016 17:19:54 +0100 Message-ID: <2368890.jTbyGqYR0M@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-34-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <20161108114953.GB15297@leverpostej> References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-3-git-send-email-yuanzhichang@hisilicon.com> <20161108114953.GB15297@leverpostej> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:5Doyxt9xi04elp421GDjh2QZHmXHdHY7fxlsbPstDfl2L3tkw+s YiTiz1qZN8AkE7i/3nEhl+2QMGgNl4AUu0FN9TTF94lGp6DrVLLPugzwqYVGRiJ+8kshR3y br1IYV9AmGMfZZv/e3bm5Iga+sL4cU8IFpSpa5+uBOyjH9f9CjDJDtQ8ZasUkVm6DuJdVyi 19LVK50XiQAvh/96w6M4A== X-UI-Out-Filterresults: notjunk:1;V01:K0:yjs9UyFIIds=:Qh89+TPYk9eopwb+NGpM8o vKnALlbhFc0lAWSyrPgxgmX0F3Ps0ChX2l57XvGQJar6NjA57wVZYiZRZzFxsSMXZ+IaUrC82 K4pFG8HOG57i8E4qyt5dDID3f99TvV7EE8Qz9HrihPBXUuX0KAFD5RrMLoghTxPsyQKuGoQre DxqTjPDPJG3dddY+nr7iJ50J6LxTeDxbDMDsbKsacw/ggRiyGflS47TWNPcEW260IBd17uMcE Nveg1WshRC9oeedeabO7aLDqys6qnjhBLYtOHCsKzrwc9oWM13RKHupYhxPhAGhPIVppXFaM5 aBFPqtTUV4NNcorvRYrgYfXy0fgphic2kdMgc2928tQAOPA2hIoiAMC73C3jPGHeIUaW9Z6Oz jVqDtfqqDHFf/1F/PeiVhLVvx8xoQh/ljFmABoG6opdb3mfFU7rNGLMcCsjimEbLRZLbe5ZYu 6dpTTtc2Sex87Xfv4rgmvoS6ensTdDH9x2BgcerfPdfiIMR8g9TybHGv7W+PL7IPpp9x/E28Y LSSjzGY32BCYjCkrjIfElRap0t0jinWqX4QRBaumooS6J3J4IpZOwYSa5rzMN6hymjUMGFmPR 8PYFl9sa/iZuhTYtNojF5E8wmxec8ED1E4RW35r1MlYVH0ZuWny4wVBXqpMjQtHtPQNm7AIyt IBfv3nir1xLYf9tF5tjFCvB79l5CZFDgqXDvyVWzkzdEkXPcF/fJ+rr2dtI4KwgcuLFpeKg/k 9BrchZzBGDgXRX5p Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday, November 8, 2016 11:49:53 AM CET Mark Rutland wrote: > On Tue, Nov 08, 2016 at 11:47:08AM +0800, zhichang.yuan wrote: > > +Hisilicon Hip06 low-pin-count device > > + Usually LPC controller is part of PCI host bridge, so the legacy ISA ports > > + locate on LPC bus can be accessed direclty. But some SoCs have independent > > + LPC controller, and access the legacy ports by triggering LPC I/O cycles. > > + Hisilicon Hip06 implements this LPC device. > > s/direclty/directly/ > > My understanding of ISA (which may be flawed) is that it's not part of > the PCI host bridge, but rather on x86 it happens to share the IO space > with PCI. On normal systems, ISA or LPC are behind a PCI bridge device, which passes down both low addresses of I/O space and memory space. > So, how about this becomes: > > Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which > provides access to some legacy ISA devices. > > I believe that we could theoretically have multiple independent LPC/ISA > busses, as is possible with PCI on !x86 systems. If the current ISA code > assumes a singleton bus, I think that's something that needs to be fixed > up more generically. > > I don't see why we should need any architecture-specific code here. Why > can we not fix up the ISA bus code in drivers/of/address.c such that it > handles multiple ISA bus instances, and translates all sub-device > addresses relative to the specific bus instance? I think it is a relatively safe assumption that there is only one ISA bridge. A lot of old drivers hardcode PIO or memory addresses when talking to an ISA device, so having multiple instances is already problematic. What is odd about ARM64 here is that the PIO space is not shared among all ISA and PCI buses in some cases. Arnd