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Subject: Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on
 multi-pci-segment arches
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: "Kroening, Gary" <gary.kroening@hpe.com>,
        "mingo@redhat.com" <mingo@redhat.com>, "hpa@zytor.com" <hpa@zytor.com>,
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From: "Liang, Kan" <kan.liang@linux.intel.com>
Message-ID: <23d70b0d-ec19-32c8-e636-4cc36f1eec47@linux.intel.com>
Date: Tue, 13 Mar 2018 13:15:52 -0400
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On 3/13/2018 12:00 PM, Andy Shevchenko wrote:
> On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
>> On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan <kan.liang@linux.intel.com> wrote:
>>
>>> +#define SKX_CAPID6             0x9c
> 
>>> +       pci_read_config_dword(dev, SKX_CAPID6, &val);
> 
> Moreover, this is too non-flexible. Can't you find a capability based
> on CAP ID  + offset?
> 

It looks it doesn't use capability.

16:1e.3 System peripheral: Intel Corporation Sky Lake-E PCU Registers 
(rev 04)
00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Thanks,
Kan