From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: Robert Foss <robert.foss@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Jonathan Marek <jonathan@marek.ca>,
Taniya Das <tdas@codeaurora.org>,
MSM <linux-arm-msm@vger.kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Vinod Koul <vinod.koul@linaro.org>
Subject: Re: [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350
Date: Thu, 17 Jun 2021 21:37:12 +0200 [thread overview]
Message-ID: <243ab835-bc91-6cc6-a9ce-7be6763dc89e@somainline.org> (raw)
In-Reply-To: <CAG3jFysRuF=xkTaPK3efDW20cQ3hXLqqsT7J5YVgYvO1dmFOvA@mail.gmail.com>
>>> +
>>> +static struct pll_vco vco_table[] = {
>>> + { 249600000, 1750000000, 0 },
>>> +};
>>> +
>>> +static const struct alpha_pll_config disp_cc_pll0_config = {
>>> + .l = 0x47,
>> Is the ".cal_l = 0x44," part from downstream not necessary?
> Yes it is. I went back and forth about 'cal_l', but in the end the
> only value it is ever set to is 0x44, which is also what the default
> value is. So there is no need for representing it explicitly at the
> moment.
Interesting, maybe it'll be required for next SoCs..
>>> +};
>>> +
>>> +static const struct alpha_pll_config disp_cc_pll1_config = {
>>> + .l = 0x1F,
>> Ditto
> Sorry, ditto what?
Aah, sorry I cut out a ".cal_l = 0x44" line while adding my comments..
Konrad
next prev parent reply other threads:[~2021-06-17 19:37 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 14:10 [RFC v1 00/11] Qcom SM8350 DispCC & VideoCC Robert Foss
2021-06-16 14:10 ` [RFC v1 01/11] clk: qcom: common: Add runtime init/suspend/resume Robert Foss
2021-06-16 14:10 ` [RFC v1 02/11] clk: qcom: rcg2: Add support for flags Robert Foss
2021-06-16 15:33 ` Konrad Dybcio
2021-06-17 7:58 ` Robert Foss
2021-06-16 16:07 ` Dmitry Baryshkov
2021-06-17 13:37 ` Robert Foss
2021-06-16 14:10 ` [RFC v1 03/11] clk: qcom: clk-alpha-pll: Fix typo in comment Robert Foss
2021-06-16 14:11 ` [RFC v1 04/11] clk: qcom: clk-alpha-pll: Add configuration support for LUCID 5LPE Robert Foss
2021-06-16 14:11 ` [RFC v1 05/11] dt-bindings: clock: Add QCOM SM8350 display clock bindings Robert Foss
2021-06-24 21:18 ` Rob Herring
2021-06-25 13:51 ` Robert Foss
2021-06-16 14:11 ` [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350 Robert Foss
2021-06-16 15:42 ` Konrad Dybcio
2021-06-17 9:02 ` Robert Foss
2021-06-17 19:37 ` Konrad Dybcio [this message]
2021-06-16 14:11 ` [RFC v1 07/11] dt-bindings: clock: Add SM8350 QCOM video clock bindings Robert Foss
2021-06-16 14:11 ` [RFC v1 08/11] clk: qcom: Add video clock controller driver for SM8350 Robert Foss
2021-06-16 14:11 ` [RFC v1 09/11] arm64: dts: qcom: sm8350: Power up dispcc & videocc on sm8350 by MMCX regulator Robert Foss
2021-06-16 14:11 ` [RFC v1 10/11] arm64: dts: qcom: sm8350: Add videocc DT node Robert Foss
2021-06-16 14:11 ` [RFC v1 11/11] arm64: dts: qcom: sm8350: Add dispcc " Robert Foss
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