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[86.58.17.133]) by smtp.gmail.com with ESMTPSA id p12sm13492367wme.43.2021.06.06.09.26.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Jun 2021 09:26:32 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, drew@beagleboard.org, liush@allwinnertech.com, lazyparser@gmail.com, wefu@redhat.com, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren , Atish Patra , Christoph Hellwig Subject: Re: [RFC PATCH v2 09/11] riscv: soc: Initial DTS for Allwinner D1 NeZha board Date: Sun, 06 Jun 2021 18:26:30 +0200 Message-ID: <2490489.OUOj5N01qN@jernej-laptop> In-Reply-To: <1622970249-50770-13-git-send-email-guoren@kernel.org> References: <1622970249-50770-1-git-send-email-guoren@kernel.org> <1622970249-50770-13-git-send-email-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi! I didn't go through all details. After you fix all comments below, you should run "make dtbs_check" and fix all reported warnings too. Dne nedelja, 06. junij 2021 ob 11:04:07 CEST je guoren@kernel.org napisal(a): > From: Guo Ren > > Add initial DTS for Allwinner D1 NeZha board having only essential > devices (uart, dummy, clock, reset, clint, plic, etc). > > Signed-off-by: Guo Ren > Co-Developed-by: Liu Shaohua > Signed-off-by: Liu Shaohua > Cc: Anup Patel > Cc: Atish Patra > Cc: Christoph Hellwig > Cc: Chen-Yu Tsai > Cc: Drew Fustini > Cc: Maxime Ripard > Cc: Palmer Dabbelt > Cc: Wei Fu > Cc: Wei Wu > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/allwinner/Makefile | 2 + > .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts | 29 ++++++++ > arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi | 84 > ++++++++++++++++++++++ 4 files changed, 116 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/Makefile > create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts > create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index fe996b8..3e7b264 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -2,5 +2,6 @@ > subdir-y += sifive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > subdir-y += microchip > +subdir-y += allwinner > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/allwinner/Makefile > b/arch/riscv/boot/dts/allwinner/Makefile new file mode 100644 > index 00000000..4adbf4b > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb > diff --git a/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts > b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file mode > 100644 > index 00000000..cd9f7c9 > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts Board DT names are comprised of soc name and board name, in this case it would be "sun20i-d1-nezha-kit.dts" > @@ -0,0 +1,29 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) Usually copyrights are added below spdx id. > + > +/dts-v1/; > + > +#include "allwinner-d1.dtsi" > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; This should be part of SoC level DTSI. > + model = "Allwinner D1 NeZha Kit"; > + compatible = "allwinner,d1-nezha-kit"; Board specific compatible string should be followed with SoC compatible, in this case "allwinner,sun20i-d1". You should document it too. > + > + chosen { > + bootargs = "console=ttyS0,115200"; Above line doesn't belong here. If anything, it should be added dynamically by bootloader. > + stdout-path = &serial0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0x0 0x40000000 0x0 0x20000000>; > + }; Ditto for whole memory node. > + > + soc { > + }; There is no point having empty nodes. > +}; > + > +&serial0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi > b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file mode 100644 > index 00000000..11cd938 > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi Current naming approach for Allwinner SoC level DTSI is "sun20i-d1.dtsi". > @@ -0,0 +1,84 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +/dts-v1/; > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; Since all peripherals and memory are below 4 GiB, why have 64-bit addresses and sizes? It just clutters DT. > + model = "Allwinner D1 Soc"; > + compatible = "allwinner,d1-nezha-kit"; Compatible and model don't belong to SoC level DTSI. > + > + chosen { > + }; Remove empty node. > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <2400000>; > + cpu@0 { > + device_type = "cpu"; > + reg = <0>; > + status = "okay"; > + compatible = "riscv"; > + riscv,isa = "rv64imafdcv"; > + mmu-type = "riscv,sv39"; > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + reset: reset-sample { > + compatible = "thead,reset-sample"; > + plic-delegate = <0x0 0x101ffffc>; > + }; > + > + clint: clint@14000000 { > + compatible = "riscv,clint0"; > + interrupts-extended = < > + &cpu0_intc 3 &cpu0_intc 7 > + >; > + reg = <0x0 0x14000000 0x0 0x04000000>; > + clint,has-no-64bit-mmio; > + }; > + > + plic: interrupt-controller@10000000 { > + #interrupt-cells = <1>; > + compatible = "riscv,plic0"; > + interrupt-controller; > + interrupts-extended = < > + &cpu0_intc 0xffffffff &cpu0_intc 9 > + >; > + reg = <0x0 0x10000000 0x0 0x04000000>; > + reg-names = "control"; > + riscv,max-priority = <7>; > + riscv,ndev = <200>; > + }; > + > + dummy_apb: apb-clock { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "dummy_apb"; > + #clock-cells = <0>; > + }; > + > + serial0: serial@2500000 { This should be uart0 and board should have alias for it. Check ARM based Allwinner DTs. Best regards, Jernej > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x02500000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <18>; > + clocks = <&dummy_apb>; > + status = "disabled"; > + }; > + }; > +};