* [v2 1/6] arm64: dts: msm8916: Add i2c-qcom-cci node
2020-03-17 13:57 [v2 0/6] Qualcomm CCI & Camera for db410c & db845c Robert Foss
@ 2020-03-17 13:57 ` Robert Foss
2020-03-17 13:57 ` [v2 2/6] arm64: dts: apq8016-sbc: Add CCI/Sensor nodes Robert Foss
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Robert Foss @ 2020-03-17 13:57 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain
Cc: Robert Foss
From: Loic Poulain <loic.poulain@linaro.org>
The msm8916 CCI controller provides one CCI/I2C bus.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Add label to cci node
- Sort cci node by address
- Relabel cci0 i2c bus to cci-i2c0
arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 9f31064f2374..1d5cb3fef906 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1584,6 +1584,33 @@
};
};
+ cci: cci@1b0c000 {
+ compatible = "qcom,msm8916-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1b0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb", "cci_ahb",
+ "cci", "camss_ahb";
+ assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>;
+ assigned-clock-rates = <80000000>, <19200000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cci0_default>;
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
smd {
compatible = "qcom,smd";
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [v2 2/6] arm64: dts: apq8016-sbc: Add CCI/Sensor nodes
2020-03-17 13:57 [v2 0/6] Qualcomm CCI & Camera for db410c & db845c Robert Foss
2020-03-17 13:57 ` [v2 1/6] arm64: dts: msm8916: Add i2c-qcom-cci node Robert Foss
@ 2020-03-17 13:57 ` Robert Foss
2020-03-17 13:57 ` [v2 3/6] arm64: dts: sdm845: Add i2c-qcom-cci node Robert Foss
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Robert Foss @ 2020-03-17 13:57 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain
Cc: Robert Foss
From: Loic Poulain <loic.poulain@linaro.org>
Add cci device to msm8916.dtsi.
Add default 96boards camera node for db410c (apq8016-sbc).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Reference CCI by label
- Don't use generic node names
- Move regulator nodes out of /soc
- Use CCI label and move node out of /soc
- Use reference for camss and move node out of /soc
- Use reference for cci-i2c0 and move out of /cci
- Disable camera_read by default, since no mezzanine board is guaranteed
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 76 +++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 037e26b3f8d5..d98c7e9e6eb9 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -51,6 +51,30 @@
stdout-path = "serial0";
};
+ camera_vdddo_1v8: camera_vdddo_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdddo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera_vdda_2v8: camera_vdda_2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdda";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ camera_vddd_1v5: camera_vddd_1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vddd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
reserved-memory {
ramoops@bff00000{
compatible = "ramoops";
@@ -538,6 +562,58 @@
};
};
+&camss {
+ status = "ok";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csiphy0_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&ov5640_ep>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+&cci {
+ status = "ok";
+};
+
+&cci_i2c0 {
+ camera_rear@3b {
+ compatible = "ovti,ov5640";
+ reg = <0x3b>;
+
+ enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_rear_default>;
+
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <23880000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ /* No camera mezzanine by default */
+ status = "disabled";
+
+ port {
+ ov5640_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+};
+
&spmi_bus {
pm8916_0: pm8916@0 {
pon@800 {
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [v2 3/6] arm64: dts: sdm845: Add i2c-qcom-cci node
2020-03-17 13:57 [v2 0/6] Qualcomm CCI & Camera for db410c & db845c Robert Foss
2020-03-17 13:57 ` [v2 1/6] arm64: dts: msm8916: Add i2c-qcom-cci node Robert Foss
2020-03-17 13:57 ` [v2 2/6] arm64: dts: apq8016-sbc: Add CCI/Sensor nodes Robert Foss
@ 2020-03-17 13:57 ` Robert Foss
2020-03-17 13:57 ` [v2 4/6] arm64: dts: sdm845-db845c: Add pm_8998 gpio names Robert Foss
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Robert Foss @ 2020-03-17 13:57 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain
Cc: Robert Foss
The sdm845 SOC ships with a CCI controller, which
has two CCI/I2C buses.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Pad addresses to 8 bytes
- Sort clock_camcc by address
- Change cciX pinctrl node names
- Remove pinmux/pinconf nodes from pinctrl nodes
- Remove clk suffix from CCI node clock-names
- Give CCI i2c-bus nodes labels
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 +
arch/arm64/boot/dts/qcom/sdm845.dtsi | 92 ++++++++++++++++++++++
2 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index eb77aaa6a819..a6b6837c3d68 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -583,3 +583,7 @@
bias-pull-up;
};
};
+
+&cci {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d42302b8889b..91a60847026f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
@@ -1451,6 +1452,42 @@
gpio-ranges = <&tlmm 0 0 150>;
wakeup-parent = <&pdc_intc>;
+ cci0_default: cci0-default {
+ /* SDA, SCL */
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci0_sleep: cci0-sleep {
+ /* SDA, SCL */
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+
+ cci1_default: cci1-default {
+ /* SDA, SCL */
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci1_sleep: cci1-sleep {
+ /* SDA, SCL */
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+
qspi_clk: qspi-clk {
pinmux {
pins = "gpio95";
@@ -2608,6 +2645,61 @@
#reset-cells = <1>;
};
+ cci: cci@ac4a000 {
+ compatible = "qcom,sdm845-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4a000 0 0x4000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+ clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&clock_camcc CAM_CC_SOC_AHB_CLK>,
+ <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+ <&clock_camcc CAM_CC_CCI_CLK>,
+ <&clock_camcc CAM_CC_CCI_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "soc_ahb",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&clock_camcc CAM_CC_CCI_CLK>;
+ assigned-clock-rates = <80000000>, <37500000>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ clock_camcc: clock-controller@ad00000 {
+ compatible = "qcom,sdm845-camcc";
+ reg = <0 0x0ad00000 0 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: mdss@ae00000 {
compatible = "qcom,sdm845-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [v2 4/6] arm64: dts: sdm845-db845c: Add pm_8998 gpio names
2020-03-17 13:57 [v2 0/6] Qualcomm CCI & Camera for db410c & db845c Robert Foss
` (2 preceding siblings ...)
2020-03-17 13:57 ` [v2 3/6] arm64: dts: sdm845: Add i2c-qcom-cci node Robert Foss
@ 2020-03-17 13:57 ` Robert Foss
2020-03-17 13:57 ` [v2 5/6] arm64: dts: sdm845-db845c: Add ov8856 & ov7251 camera nodes Robert Foss
2020-03-17 13:57 ` [v2 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers Robert Foss
5 siblings, 0 replies; 9+ messages in thread
From: Robert Foss @ 2020-03-17 13:57 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain
Cc: Robert Foss
Add pm_8998 GPIO trace names. These names are defined in
the 96boards db845c mezzanine schematic.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Move gpio-names to previous reference to pm8998_gpio label
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index a6b6837c3d68..efb0086e2aa1 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -365,6 +365,34 @@
};
&pm8998_gpio {
+ gpio-line-names =
+ "NC",
+ "NC",
+ "WLAN_SW_CTRL",
+ "NC",
+ "PM_GPIO5_BLUE_BT_LED",
+ "VOL_UP_N",
+ "NC",
+ "ADC_IN1",
+ "PM_GPIO9_YEL_WIFI_LED",
+ "CAM0_AVDD_EN",
+ "NC",
+ "CAM0_DVDD_EN",
+ "PM_GPIO13_GREEN_U4_LED",
+ "DIV_CLK2",
+ "NC",
+ "NC",
+ "NC",
+ "SMB_STAT",
+ "NC",
+ "NC",
+ "ADC_IN2",
+ "OPTION1",
+ "WCSS_PWR_REQ",
+ "PM845_GPIO24",
+ "OPTION2",
+ "PM845_SLB";
+
vol_up_pin_a: vol-up-active {
pins = "gpio6";
function = "normal";
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [v2 5/6] arm64: dts: sdm845-db845c: Add ov8856 & ov7251 camera nodes
2020-03-17 13:57 [v2 0/6] Qualcomm CCI & Camera for db410c & db845c Robert Foss
` (3 preceding siblings ...)
2020-03-17 13:57 ` [v2 4/6] arm64: dts: sdm845-db845c: Add pm_8998 gpio names Robert Foss
@ 2020-03-17 13:57 ` Robert Foss
2020-03-17 13:57 ` [v2 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers Robert Foss
5 siblings, 0 replies; 9+ messages in thread
From: Robert Foss @ 2020-03-17 13:57 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain
Cc: Robert Foss
Enable the ov8856 main camera and the ov7251 b/w tracking camera
used on the Qualcomm RB3 kit.
Currently the camera nodes have not yet been attached to an to a
CSI2 endpoint, since no driver currently supports the ISP that the the
SDM845/db845c ships with.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Move cam0_ pinctrls subnodes into the first pm8998_gpio reference
- Remove accidentally committed &tlmn node subnodes
- Remove redundant tlmm pinctrl subnodes
- Fix pinctrl subnode identation
- Remove accidentally committed &tlmn node subnodes
- Replace underscores in node names
- Reference cci i2c buses by labe
- Change camera node names from camX@YY to camera@YY
- Remove camera@10 comment about I2C addresses
- Replace GPIO_ACTIVE_HIGH with 0 in camera nodes
- Removed extra newline
- Remove comment about not being available always
- Disable cameras as CSI driver is missing
- Fix factual error in comment about vreg_s4a_1p8
- Remove dummy regulator cam3_vddd_1v2
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 178 +++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index efb0086e2aa1..ed71278196f2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -110,6 +110,40 @@
// enable-active-high;
};
+ cam0_dvdd_1v2: reg_cam0_dvdd_1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM0_DVDD_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ enable-active-high;
+ gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam0_dvdd_1v2_en_default>;
+ vin-supply = <&vbat>;
+ };
+
+ cam0_avdd_2v8: reg_cam0_avdd_2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM0_AVDD_2V8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam0_avdd_2v8_en_default>;
+ vin-supply = <&vbat>;
+ };
+
+ /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */
+ cam3_avdd_2v8: reg_cam3_avdd_2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM3_AVDD_2V8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ vin-supply = <&vbat>;
+ };
+
pcie0_3p3v_dual: vldo-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "VLDO_3V3";
@@ -393,6 +427,24 @@
"OPTION2",
"PM845_SLB";
+ cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en {
+ pins = "gpio12";
+ function = "normal";
+
+ bias-pull-up;
+ drive-push-pull;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ };
+
+ cam0_avdd_2v8_en_default: cam0-avdd-2v8-en {
+ pins = "gpio10";
+ function = "normal";
+
+ bias-pull-up;
+ drive-push-pull;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ };
+
vol_up_pin_a: vol-up-active {
pins = "gpio6";
function = "normal";
@@ -434,6 +486,42 @@
};
&tlmm {
+ cam0_default: cam0_default {
+ rst {
+ pins = "gpio9";
+ function = "gpio";
+
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk0 {
+ pins = "gpio13";
+ function = "cam_mclk";
+
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cam3_default: cam3_default {
+ rst {
+ function = "gpio";
+ pins = "gpio21";
+
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk3 {
+ function = "cam_mclk";
+ pins = "gpio16";
+
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
pcie0_pwren_state: pcie0-pwren {
pins = "gpio90";
function = "gpio";
@@ -612,6 +700,96 @@
};
};
+&pm8998_gpio {
+
+};
+
&cci {
status = "ok";
};
+
+&cci_i2c0 {
+ camera@10 {
+ compatible = "ovti,ov8856";
+ reg = <0x10>;
+
+ // CAM0_RST_N
+ reset-gpios = <&tlmm 9 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam0_default>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 9 0>;
+
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "xvclk";
+ clock-frequency = <19200000>;
+
+ /* The &vreg_s4a_1p8 trace is powered on as a,
+ * so it is represented by a fixed regulator.
+ *
+ * The 2.8V vdda-supply and 1.2V vddd-supply regulators
+ * both have to be enabled through the power management
+ * gpios.
+ */
+ power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+ dovdd-supply = <&vreg_lvs1a_1p8>;
+ avdd-supply = <&cam0_avdd_2v8>;
+ dvdd-supply = <&cam0_dvdd_1v2>;
+
+ status = "disable";
+
+ port {
+ ov8856_ep: endpoint {
+ clock-lanes = <1>;
+ link-frequencies = /bits/ 64
+ <360000000 180000000>;
+ data-lanes = <1 2 3 4>;
+// remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+};
+
+&cci_i2c1 {
+ camera@60 {
+ compatible = "ovti,ov7251";
+
+ // I2C address as per ov7251.txt linux documentation
+ reg = <0x60>;
+
+ // CAM3_RST_N
+ enable-gpios = <&tlmm 21 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam3_default>;
+ gpios = <&tlmm 16 0>,
+ <&tlmm 21 0>;
+
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ /* The &vreg_s4a_1p8 trace always powered on.
+ *
+ * The 2.8V vdda-supply regulator is enabled when the
+ * vreg_s4a_1p8 trace is pulled high.
+ * It too is represented by a fixed regulator.
+ *
+ * No 1.2V vddd-supply regulator is used.
+ */
+ power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+ vdddo-supply = <&vreg_lvs1a_1p8>;
+ vdda-supply = <&cam3_avdd_2v8>;
+
+ status = "disable";
+
+ port {
+ ov7251_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 1>;
+// remote-endpoint = <&csiphy3_ep>;
+ };
+ };
+ };
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [v2 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers
2020-03-17 13:57 [v2 0/6] Qualcomm CCI & Camera for db410c & db845c Robert Foss
` (4 preceding siblings ...)
2020-03-17 13:57 ` [v2 5/6] arm64: dts: sdm845-db845c: Add ov8856 & ov7251 camera nodes Robert Foss
@ 2020-03-17 13:57 ` Robert Foss
2020-03-20 19:52 ` Luca Weiss
5 siblings, 1 reply; 9+ messages in thread
From: Robert Foss @ 2020-03-17 13:57 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain
Cc: Robert Foss
Build camera clock, isp and controller drivers as modules.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4db223dbc549..7cb6989249ab 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -376,6 +376,7 @@ CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_OWL=y
CONFIG_I2C_PXA=y
+CONFIG_I2C_QCOM_CCI=m
CONFIG_I2C_QCOM_GENI=m
CONFIG_I2C_QUP=y
CONFIG_I2C_RK3X=y
@@ -530,6 +531,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_RENESAS_FCP=m
CONFIG_VIDEO_RENESAS_VSP1=m
+CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_DRM=m
CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_NOUVEAU=m
@@ -732,6 +734,7 @@ CONFIG_MSM_GCC_8994=y
CONFIG_MSM_MMCC_8996=y
CONFIG_MSM_GCC_8998=y
CONFIG_QCS_GCC_404=y
+CONFIG_SDM_CAMCC_845=m
CONFIG_SDM_GCC_845=y
CONFIG_SM_GCC_8150=y
CONFIG_QCOM_HFPLL=y
@@ -762,6 +765,7 @@ CONFIG_QCOM_COMMAND_DB=y
CONFIG_QCOM_GENI_SE=y
CONFIG_QCOM_GLINK_SSR=m
CONFIG_QCOM_RMTFS_MEM=m
+CONFIG_SDM_CAMCC_845=m
CONFIG_QCOM_RPMH=y
CONFIG_QCOM_RPMHPD=y
CONFIG_QCOM_SMEM=y
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [v2 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers
2020-03-17 13:57 ` [v2 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers Robert Foss
@ 2020-03-20 19:52 ` Luca Weiss
2020-03-24 15:38 ` Robert Foss
0 siblings, 1 reply; 9+ messages in thread
From: Luca Weiss @ 2020-03-20 19:52 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mark.rutland, catalin.marinas,
will, shawnguo, olof, maxime, Anson.Huang, dinguyen,
leonard.crestez, marcin.juszkiewicz, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, Loic Poulain, Robert Foss
Cc: Robert Foss
Hi Robert,
On Dienstag, 17. März 2020 14:57:40 CET Robert Foss wrote:
> Build camera clock, isp and controller drivers as modules.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 4db223dbc549..7cb6989249ab 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -376,6 +376,7 @@ CONFIG_I2C_MESON=y
> CONFIG_I2C_MV64XXX=y
> CONFIG_I2C_OWL=y
> CONFIG_I2C_PXA=y
> +CONFIG_I2C_QCOM_CCI=m
> CONFIG_I2C_QCOM_GENI=m
> CONFIG_I2C_QUP=y
> CONFIG_I2C_RK3X=y
> @@ -530,6 +531,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
> CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
> CONFIG_VIDEO_RENESAS_FCP=m
> CONFIG_VIDEO_RENESAS_VSP1=m
> +CONFIG_VIDEO_QCOM_CAMSS=m
> CONFIG_DRM=m
> CONFIG_DRM_I2C_NXP_TDA998X=m
> CONFIG_DRM_NOUVEAU=m
> @@ -732,6 +734,7 @@ CONFIG_MSM_GCC_8994=y
> CONFIG_MSM_MMCC_8996=y
> CONFIG_MSM_GCC_8998=y
> CONFIG_QCS_GCC_404=y
> +CONFIG_SDM_CAMCC_845=m
You seem to have this option twice in this patch.
> CONFIG_SDM_GCC_845=y
> CONFIG_SM_GCC_8150=y
> CONFIG_QCOM_HFPLL=y
> @@ -762,6 +765,7 @@ CONFIG_QCOM_COMMAND_DB=y
> CONFIG_QCOM_GENI_SE=y
> CONFIG_QCOM_GLINK_SSR=m
> CONFIG_QCOM_RMTFS_MEM=m
> +CONFIG_SDM_CAMCC_845=m
^
> CONFIG_QCOM_RPMH=y
> CONFIG_QCOM_RPMHPD=y
> CONFIG_QCOM_SMEM=y
Regards
Luca
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [v2 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers
2020-03-20 19:52 ` Luca Weiss
@ 2020-03-24 15:38 ` Robert Foss
0 siblings, 0 replies; 9+ messages in thread
From: Robert Foss @ 2020-03-24 15:38 UTC (permalink / raw)
To: Luca Weiss
Cc: agross, Bjorn Andersson, Rob Herring, Mark Rutland,
catalin.marinas, will, shawnguo, olof, maxime, Anson.Huang,
dinguyen, leonard.crestez, Marcin Juszkiewicz, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Loic Poulain
Hey Luca,
On Fri, 20 Mar 2020 at 20:52, Luca Weiss <luca@z3ntu.xyz> wrote:
>
> Hi Robert,
>
> On Dienstag, 17. März 2020 14:57:40 CET Robert Foss wrote:
> > Build camera clock, isp and controller drivers as modules.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> > arch/arm64/configs/defconfig | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> > index 4db223dbc549..7cb6989249ab 100644
> > --- a/arch/arm64/configs/defconfig
> > +++ b/arch/arm64/configs/defconfig
> > @@ -376,6 +376,7 @@ CONFIG_I2C_MESON=y
> > CONFIG_I2C_MV64XXX=y
> > CONFIG_I2C_OWL=y
> > CONFIG_I2C_PXA=y
> > +CONFIG_I2C_QCOM_CCI=m
> > CONFIG_I2C_QCOM_GENI=m
> > CONFIG_I2C_QUP=y
> > CONFIG_I2C_RK3X=y
> > @@ -530,6 +531,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
> > CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
> > CONFIG_VIDEO_RENESAS_FCP=m
> > CONFIG_VIDEO_RENESAS_VSP1=m
> > +CONFIG_VIDEO_QCOM_CAMSS=m
> > CONFIG_DRM=m
> > CONFIG_DRM_I2C_NXP_TDA998X=m
> > CONFIG_DRM_NOUVEAU=m
> > @@ -732,6 +734,7 @@ CONFIG_MSM_GCC_8994=y
> > CONFIG_MSM_MMCC_8996=y
> > CONFIG_MSM_GCC_8998=y
> > CONFIG_QCS_GCC_404=y
> > +CONFIG_SDM_CAMCC_845=m
>
> You seem to have this option twice in this patch.
Thanks for catching this.
I'll send out a fix in v3.
>
> > CONFIG_SDM_GCC_845=y
> > CONFIG_SM_GCC_8150=y
> > CONFIG_QCOM_HFPLL=y
> > @@ -762,6 +765,7 @@ CONFIG_QCOM_COMMAND_DB=y
> > CONFIG_QCOM_GENI_SE=y
> > CONFIG_QCOM_GLINK_SSR=m
> > CONFIG_QCOM_RMTFS_MEM=m
> > +CONFIG_SDM_CAMCC_845=m
>
> ^
>
> > CONFIG_QCOM_RPMH=y
> > CONFIG_QCOM_RPMHPD=y
> > CONFIG_QCOM_SMEM=y
>
> Regards
> Luca
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread