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b=Q0OBVYHusDL0GbmEZ8/l4wHPAyJGAF9vDPbgeM590zrFSU4XgzHvBfgmXHDC/THyNYjVNGXAr5q2D46BmSQjEOfromQEg+T49zvQif4adzvqO56tOvndtvpvDWDDNeB5M4C73qi1Pkz1eUsyuS++CHyH5ExFwQmDD68Xw+urqUo= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) by CH2PR12MB4953.namprd12.prod.outlook.com (2603:10b6:610:36::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.10; Fri, 2 Dec 2022 16:58:23 +0000 Received: from MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::ff3c:2d37:75f3:442a]) by MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::ff3c:2d37:75f3:442a%4]) with mapi id 15.20.5880.010; Fri, 2 Dec 2022 16:58:23 +0000 Message-ID: <25462433-6c0b-ac6a-888e-0c42c3e045de@amd.com> Date: Fri, 2 Dec 2022 10:58:21 -0600 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH v6 01/11] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Content-Language: en-US To: Perry Yuan , rafael.j.wysocki@intel.com, ray.huang@amd.com, viresh.kumar@linaro.org Cc: Deepak.Sharma@amd.com, Nathan.Fontenot@amd.com, Alexander.Deucher@amd.com, Shimmer.Huang@amd.com, Xiaojian.Du@amd.com, Li.Meng@amd.com, wyes.karny@amd.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221202074719.623673-1-perry.yuan@amd.com> <20221202074719.623673-2-perry.yuan@amd.com> From: "Limonciello, Mario" In-Reply-To: <20221202074719.623673-2-perry.yuan@amd.com> Content-Type: text/plain; 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On 12/2/2022 01:47, Perry Yuan wrote: > From: Perry Yuan > > Add support for setting and querying EPP preferences to the generic > CPPC driver. This enables downstream drivers such as amd-pstate to discover > and use these values > > In order to get EPP worked, cppc_get_epp_caps() will query EPP preference > value and cppc_set_epp_perf() will set EPP new value. > Before the EPP works, pstate driver will use cppc_set_auto_epp() to > enable EPP function from firmware firstly. My suggestion at rewording this: Downstream drivers that want to use the new symbols cppc_get_epp_caps and cppc_set_epp_perf for querying and setting EPP preferences will need to call cppc_set_auto_epp to enable the EPP function first. > > Signed-off-by: Perry Yuan > --- > drivers/acpi/cppc_acpi.c | 114 +++++++++++++++++++++++++++++++++++++-- > include/acpi/cppc_acpi.h | 12 +++++ > 2 files changed, 121 insertions(+), 5 deletions(-) > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c > index 093675b1a1ff..37fa75f25f62 100644 > --- a/drivers/acpi/cppc_acpi.c > +++ b/drivers/acpi/cppc_acpi.c > @@ -1093,6 +1093,9 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) > { > struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); > struct cpc_register_resource *reg; > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); > + struct cppc_pcc_data *pcc_ss_data = NULL; > + int ret = -EINVAL; > > if (!cpc_desc) { > pr_debug("No CPC descriptor for CPU:%d\n", cpunum); > @@ -1102,10 +1105,6 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) > reg = &cpc_desc->cpc_regs[reg_idx]; > > if (CPC_IN_PCC(reg)) { > - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); > - struct cppc_pcc_data *pcc_ss_data = NULL; > - int ret = 0; > - > if (pcc_ss_id < 0) > return -EIO; > > @@ -1125,7 +1124,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) > > cpc_read(cpunum, reg, perf); > > - return 0; > + return ret; > } > > /** > @@ -1365,6 +1364,111 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) > } > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); > > +/** > + * cppc_get_epp_caps - Get the energy preference register value. > + * @cpunum: CPU from which to get epp preference level. > + * @perf_caps: Return address. > + * > + * Return: 0 for success, -EIO otherwise. > + */ > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) > +{ > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); > + struct cpc_register_resource *energy_perf_reg; > + u64 energy_perf; > + > + if (!cpc_desc) { > + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); > + return -ENODEV; > + } > + > + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; > + > + if (!CPC_SUPPORTED(energy_perf_reg)) > + pr_warn_once("energy perf reg update is unsupported!\n"); > + > + if (CPC_IN_PCC(energy_perf_reg)) { > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); > + struct cppc_pcc_data *pcc_ss_data = NULL; > + int ret = 0; > + > + if (pcc_ss_id < 0) > + return -ENODEV; > + > + pcc_ss_data = pcc_data[pcc_ss_id]; > + > + down_write(&pcc_ss_data->pcc_lock); > + > + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { > + cpc_read(cpunum, energy_perf_reg, &energy_perf); > + perf_caps->energy_perf = energy_perf; > + } else { > + ret = -EIO; > + } > + > + up_write(&pcc_ss_data->pcc_lock); > + > + return ret; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps); > + > +/* > + * Set Energy Performance Preference Register value through > + * Performance Controls Interface > + */ > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) > +{ > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); > + struct cpc_register_resource *epp_set_reg; > + struct cpc_register_resource *auto_sel_reg; > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); > + struct cppc_pcc_data *pcc_ss_data = NULL; > + int ret = -EINVAL; > + > + if (!cpc_desc) { > + pr_debug("No CPC descriptor for CPU:%d\n", cpu); > + return -ENODEV; > + } > + > + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; > + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; > + > + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { > + if (pcc_ss_id < 0) { > + pr_debug("Invalid pcc_ss_id\n"); > + return -ENODEV; > + } > + > + if (CPC_SUPPORTED(auto_sel_reg)) { > + ret = cpc_write(cpu, auto_sel_reg, enable); > + if (ret) > + return ret; > + } > + > + if (CPC_SUPPORTED(epp_set_reg)) { > + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); > + if (ret) > + return ret; > + } > + > + pcc_ss_data = pcc_data[pcc_ss_id]; > + > + down_write(&pcc_ss_data->pcc_lock); > + /* after writing CPC, transfer the ownership of PCC to platform */ > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); > + up_write(&pcc_ss_data->pcc_lock); > + } else { > + ret = -ENOTSUPP; > + pr_debug("_CPC in PCC is not supported\n"); > + } > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); > + > /** > * cppc_set_enable - Set to enable CPPC on the processor by writing the > * Continuous Performance Control package EnableRegister field. > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h > index c5614444031f..a45bb876a19c 100644 > --- a/include/acpi/cppc_acpi.h > +++ b/include/acpi/cppc_acpi.h > @@ -108,12 +108,14 @@ struct cppc_perf_caps { > u32 lowest_nonlinear_perf; > u32 lowest_freq; > u32 nominal_freq; > + u32 energy_perf; > }; > > struct cppc_perf_ctrls { > u32 max_perf; > u32 min_perf; > u32 desired_perf; > + u32 energy_perf; > }; > > struct cppc_perf_fb_ctrs { > @@ -149,6 +151,8 @@ extern bool cpc_ffh_supported(void); > extern bool cpc_supported_by_cpu(void); > extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); > extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); > +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps); > +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); > #else /* !CONFIG_ACPI_CPPC_LIB */ > static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) > { > @@ -202,6 +206,14 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) > { > return -ENOTSUPP; > } > +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) > +{ > + return -ENOTSUPP; > +} > +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) > +{ > + return -ENOTSUPP; > +} > #endif /* !CONFIG_ACPI_CPPC_LIB */ > > #endif /* _CPPC_ACPI_H*/