From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 234D0C432BE for ; Mon, 9 Aug 2021 12:39:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED1CE61002 for ; Mon, 9 Aug 2021 12:39:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235528AbhHIMjT (ORCPT ); Mon, 9 Aug 2021 08:39:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235495AbhHIMjP (ORCPT ); Mon, 9 Aug 2021 08:39:15 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDA65C0613D3; Mon, 9 Aug 2021 05:38:54 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id s22-20020a17090a1c16b0290177caeba067so34371869pjs.0; Mon, 09 Aug 2021 05:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jWnjTolsyQJJUJtgYHQ22qVQAWFYBt5fDLJYF+RU014=; b=pQElWxfJa68iSq2Tsu2KXKUTilsCnqRXtKQAObZ9awnIVdINjAhYeGyCxX3QLNq6cV GA6UzdGQd/kpwwFT4dENJtZN+GAuMPBPG8k70bh/Yt+i0xgjq7SkjGHIrHVHzH158hut KTdO+W00GC6WceljhVzpGa0bqN8KvYnA/fqjKrMjrSQg9v62FUKqyz9nz0BwWdKuYmFR 77/PTG6k4nAFO7nKl/Mlb0uVKnv145Iwtdwdwub+hQs1M8wGZiUoy0gPxsbUlnll7M5k lpCxN3RobC+0K04Shvi9I+ayDNV7SZA7ruIl5htr3mnX5XwN+WXGYAi7s/h8bCgFg49b 31ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jWnjTolsyQJJUJtgYHQ22qVQAWFYBt5fDLJYF+RU014=; b=XFiQbTSmt6Hgb+Xqza/Lr4yZ4jE/7Rmqhhp3hAlzt/rjKtt4L3NJ/gRbYxnRXWqR0R Ad/+vF2ELe3p7aAxCImoBAuC16TaH+kH2wkOR/0Qu/VSKhsLcHmalvENQy2/JIcfBNRe FJQptnwgtPYA4PKnWwYUK2qYEZYS4dqARZk5wmIzJRNgnHOkLrPMdsjzbHh+az0mirgA Gfw/VRbzf1g+eMxhoTMvOOq88wOpehBPSm9m/5PR0tDJaOKB8dG9XK5r3elhlVcO6DdW HfSbyX7NE3c3bokdCsrcSgMeJCR3AD2Z53c+Z5FCzVp2CeK/CCOFJn/TQGCjyBOKR0ev 4moQ== X-Gm-Message-State: AOAM530vHzKPC8s77/o2zEtJBQ/32Xr0gRMIRy5+24G6tLgvADnD3E4u ahFouBidcouN9xnMFaU66ZE= X-Google-Smtp-Source: ABdhPJxIxZ0iLRdkZ9HiaF/N39oYGVRqBgUETiY9376+vsdcHODZHWI4mZTilWktU0YoFFgqFkErWQ== X-Received: by 2002:a63:40c1:: with SMTP id n184mr26890pga.74.1628512734354; Mon, 09 Aug 2021 05:38:54 -0700 (PDT) Received: from localhost.localdomain ([156.146.35.76]) by smtp.gmail.com with ESMTPSA id e35sm22382177pjk.28.2021.08.09.05.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 05:38:53 -0700 (PDT) From: William Breathitt Gray To: jic23@kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com, kernel@pengutronix.de, a.fatoum@pengutronix.de, kamel.bouhara@bootlin.com, gwendal@chromium.org, alexandre.belloni@bootlin.com, david@lechnology.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, syednwaris@gmail.com, patrick.havelange@essensium.com, fabrice.gasnier@st.com, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, o.rempel@pengutronix.de, jarkko.nikula@linux.intel.com, William Breathitt Gray Subject: [PATCH v15 12/13] counter: 104-quad-8: Replace mutex with spinlock Date: Mon, 9 Aug 2021 21:37:37 +0900 Message-Id: <25d7b0c6a64bcc856e875630dbd65a3da831f269.1628511445.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch replaces the mutex I/O lock with a spinlock. This is in preparation for a subsequent patch adding IRQ support for 104-QUAD-8 devices; we can't sleep in an interrupt context, so we'll need to use a spinlock instead. Acked-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 89 +++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 37 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index c587f295d720..a56751bf1e9b 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -16,6 +16,7 @@ #include #include #include +#include #define QUAD8_EXTENT 32 @@ -43,7 +44,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); * @base: base port address of the device */ struct quad8 { - struct mutex lock; + spinlock_t lock; struct counter_device counter; unsigned int fck_prescaler[QUAD8_NUM_COUNTERS]; unsigned int preset[QUAD8_NUM_COUNTERS]; @@ -124,6 +125,7 @@ static int quad8_count_read(struct counter_device *counter, unsigned int flags; unsigned int borrow; unsigned int carry; + unsigned long irqflags; int i; flags = inb(base_offset + 1); @@ -133,7 +135,7 @@ static int quad8_count_read(struct counter_device *counter, /* Borrow XOR Carry effectively doubles count range */ *val = (unsigned long)(borrow ^ carry) << 24; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer; transfer Counter to Output Latch */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, @@ -142,7 +144,7 @@ static int quad8_count_read(struct counter_device *counter, for (i = 0; i < 3; i++) *val |= (unsigned long)inb(base_offset) << (8 * i); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -152,13 +154,14 @@ static int quad8_count_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int base_offset = priv->base + 2 * count->id; + unsigned long irqflags; int i; /* Only 24-bit values are supported */ if (val > 0xFFFFFF) return -ERANGE; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); @@ -183,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter, /* Reset Error flag */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -201,8 +204,9 @@ static int quad8_function_read(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int id = count->id; + unsigned long irqflags; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); if (priv->quadrature_mode[id]) switch (priv->quadrature_scale[id]) { @@ -219,7 +223,7 @@ static int quad8_function_read(struct counter_device *counter, else *function = COUNTER_FUNCTION_PULSE_DIRECTION; - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -234,10 +238,11 @@ static int quad8_function_write(struct counter_device *counter, unsigned int *const scale = priv->quadrature_scale + id; unsigned int *const synchronous_mode = priv->synchronous_mode + id; const int base_offset = priv->base + 2 * id + 1; + unsigned long irqflags; unsigned int mode_cfg; unsigned int idr_cfg; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); mode_cfg = priv->count_mode[id] << 1; idr_cfg = priv->index_polarity[id] << 1; @@ -272,7 +277,7 @@ static int quad8_function_write(struct counter_device *counter, break; default: /* should never reach this path */ - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } } @@ -280,7 +285,7 @@ static int quad8_function_write(struct counter_device *counter, /* Load mode configuration to Counter Mode Register */ outb(QUAD8_CTR_CMR | mode_cfg, base_offset); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -406,9 +411,10 @@ static int quad8_index_polarity_set(struct counter_device *counter, struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id - 16; const int base_offset = priv->base + 2 * channel_id + 1; + unsigned long irqflags; unsigned int idr_cfg = index_polarity << 1; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); idr_cfg |= priv->synchronous_mode[channel_id]; @@ -417,7 +423,7 @@ static int quad8_index_polarity_set(struct counter_device *counter, /* Load Index Control configuration to Index Control Register */ outb(QUAD8_CTR_IDR | idr_cfg, base_offset); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -446,15 +452,16 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id - 16; const int base_offset = priv->base + 2 * channel_id + 1; + unsigned long irqflags; unsigned int idr_cfg = synchronous_mode; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); idr_cfg |= priv->index_polarity[channel_id] << 1; /* Index function must be non-synchronous in non-quadrature mode */ if (synchronous_mode && !priv->quadrature_mode[channel_id]) { - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } @@ -463,7 +470,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, /* Load Index Control configuration to Index Control Register */ outb(QUAD8_CTR_IDR | idr_cfg, base_offset); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -510,6 +517,7 @@ static int quad8_count_mode_write(struct counter_device *counter, unsigned int count_mode; unsigned int mode_cfg; const int base_offset = priv->base + 2 * count->id + 1; + unsigned long irqflags; /* Map Generic Counter count mode to 104-QUAD-8 count mode */ switch (cnt_mode) { @@ -530,7 +538,7 @@ static int quad8_count_mode_write(struct counter_device *counter, return -EINVAL; } - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); priv->count_mode[count->id] = count_mode; @@ -544,7 +552,7 @@ static int quad8_count_mode_write(struct counter_device *counter, /* Load mode configuration to Counter Mode Register */ outb(QUAD8_CTR_CMR | mode_cfg, base_offset); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -564,9 +572,10 @@ static int quad8_count_enable_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int base_offset = priv->base + 2 * count->id; + unsigned long irqflags; unsigned int ior_cfg; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); priv->ab_enable[count->id] = enable; @@ -575,7 +584,7 @@ static int quad8_count_enable_write(struct counter_device *counter, /* Load I/O control configuration */ outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -626,16 +635,17 @@ static int quad8_count_preset_write(struct counter_device *counter, struct counter_count *count, u64 preset) { struct quad8 *const priv = counter->priv; + unsigned long irqflags; /* Only 24-bit values are supported */ if (preset > 0xFFFFFF) return -ERANGE; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); quad8_preset_register_set(priv, count->id, preset); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -644,8 +654,9 @@ static int quad8_count_ceiling_read(struct counter_device *counter, struct counter_count *count, u64 *ceiling) { struct quad8 *const priv = counter->priv; + unsigned long irqflags; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); /* Range Limit and Modulo-N count modes use preset value as ceiling */ switch (priv->count_mode[count->id]) { @@ -659,7 +670,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter, break; } - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -668,23 +679,24 @@ static int quad8_count_ceiling_write(struct counter_device *counter, struct counter_count *count, u64 ceiling) { struct quad8 *const priv = counter->priv; + unsigned long irqflags; /* Only 24-bit values are supported */ if (ceiling > 0xFFFFFF) return -ERANGE; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); /* Range Limit and Modulo-N count modes use preset value as ceiling */ switch (priv->count_mode[count->id]) { case 1: case 3: quad8_preset_register_set(priv, count->id, ceiling); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } @@ -706,12 +718,13 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int base_offset = priv->base + 2 * count->id + 1; + unsigned long irqflags; unsigned int ior_cfg; /* Preset enable is active low in Input/Output Control register */ preset_enable = !preset_enable; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); priv->preset_enable[count->id] = preset_enable; @@ -720,7 +733,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, /* Load I/O control configuration to Input / Output Control Register */ outb(QUAD8_CTR_IOR | ior_cfg, base_offset); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -731,22 +744,23 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id / 2; + unsigned long irqflags; bool disabled; unsigned int status; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); disabled = !(priv->cable_fault_enable & BIT(channel_id)); if (disabled) { - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } /* Logic 0 = cable fault */ status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); /* Mask respective channel and invert logic */ *cable_fault = !(status & BIT(channel_id)); @@ -772,9 +786,10 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id / 2; + unsigned long irqflags; unsigned int cable_fault_enable; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); if (enable) priv->cable_fault_enable |= BIT(channel_id); @@ -786,7 +801,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -809,8 +824,9 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id / 2; const int base_offset = priv->base + 2 * channel_id; + unsigned long irqflags; - mutex_lock(&priv->lock); + spin_lock_irqsave(&priv->lock, irqflags); priv->fck_prescaler[channel_id] = prescaler; @@ -822,7 +838,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, base_offset + 1); - mutex_unlock(&priv->lock); + spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -991,8 +1007,7 @@ static int quad8_probe(struct device *dev, unsigned int id) priv->counter.priv = priv; priv->base = base[id]; - /* Initialize mutex */ - mutex_init(&priv->lock); + spin_lock_init(&priv->lock); /* Reset all counters and disable interrupt function */ outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); -- 2.32.0