From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: linuxarm@huawei.com, mauro.chehab@huawei.com,
Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jingoo Han <jingoohan1@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH v5 2/5] dt-bindings: PCI: add snps,dw-pcie-ep.yaml
Date: Sun, 18 Jul 2021 13:40:49 +0200 [thread overview]
Message-ID: <26025b256232c2e4bd91954907b9d92db27199a3.1626608375.git.mchehab+huawei@kernel.org> (raw)
In-Reply-To: <cover.1626608375.git.mchehab+huawei@kernel.org>
Currently, the designware schema is defined on a text file:
designware-pcie.txt
It contains two separate schemas on it:
- snps,dw-pcie
This one uses the pci-bus.yaml schema;
- snps,dw-pcie-ep
This one uses the pci-ep.yaml schema.
As the:
AllOf:
- $ref: <foo>
for the endpoint part is different than the PCI one, place
it on a separate yaml file.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../bindings/pci/snps,dw-pcie-ep.yaml | 90 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
new file mode 100644
index 000000000000..b5935b1b153f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe endpoint interface
+
+maintainers:
+ - Jingoo Han <jingoohan1@gmail.com>
+ - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+
+description: |
+ Synopsys DesignWare PCIe host controller endpoint
+
+allOf:
+ - $ref: /schemas/pci/pci-ep.yaml#
+
+properties:
+ compatible:
+ anyOf:
+ - {}
+ - const: snps,dw-pcie-ep
+
+ reg:
+ description: |
+ It should contain Data Bus Interface (dbi) and config registers for all
+ versions.
+ For designware core version >= 4.80, it may contain ATU address space.
+ minItems: 2
+ maxItems: 4
+
+ reg-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
+
+ reset-gpio:
+ description: GPIO pin number of PERST# signal
+ maxItems: 1
+ deprecated: true
+
+ reset-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ snps,enable-cdm-check:
+ type: boolean
+ description: |
+ This is a boolean property and if present enables
+ automatic checking of CDM (Configuration Dependent Module) registers
+ for data corruption. CDM registers include standard PCIe configuration
+ space registers, Port Logic registers, DMA and iATU (internal Address
+ Translation Unit) registers.
+
+ num-ib-windows:
+ description: number of inbound address translation windows
+ maxItems: 1
+ deprecated: true
+
+ num-ob-windows:
+ description: number of outbound address translation windows
+ maxItems: 1
+ deprecated: true
+
+ max-functions:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: maximum number of functions that can be configured
+
+required:
+ - reg
+ - reg-names
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pcie-ep@dfd00000 {
+ compatible = "snps,dw-pcie-ep";
+ reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
+ <0xdfc01000 0x0001000>, /* IP registers 2 */
+ <0xd0000000 0x2000000>; /* Configuration space */
+ reg-names = "dbi", "dbi2", "addr_space";
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index c88f6cb37e47..5818733eace7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14307,6 +14307,7 @@ L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/designware-pcie.txt
F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
F: drivers/pci/controller/dwc/*designware*
PCI DRIVER FOR TI DRA7XX/J721E
--
2.31.1
next prev parent reply other threads:[~2021-07-18 11:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-18 11:40 [PATCH v5 0/5] convert designware-pcie.txt to yaml Mauro Carvalho Chehab
2021-07-18 11:40 ` [PATCH v5 1/5] dt-bindings: PCI: add snps,dw-pcie.yaml Mauro Carvalho Chehab
2021-07-19 22:02 ` Rob Herring
2021-07-18 11:40 ` Mauro Carvalho Chehab [this message]
2021-07-19 22:02 ` [PATCH v5 2/5] dt-bindings: PCI: add snps,dw-pcie-ep.yaml Rob Herring
2021-07-18 11:40 ` [PATCH v5 3/5] dt-bindings: PCI: update references to Designware schema Mauro Carvalho Chehab
2021-07-19 22:02 ` Rob Herring
2021-07-18 11:40 ` [PATCH v5 4/5] dt-bindings: PCI: remove designware-pcie.txt Mauro Carvalho Chehab
2021-07-19 22:02 ` Rob Herring
2021-07-18 11:40 ` [PATCH v5 5/5] dt-bindings: arm64: tegra: fix pcie-ep DT nodes Mauro Carvalho Chehab
2021-07-19 21:19 ` Rob Herring
2021-10-07 19:23 ` Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=26025b256232c2e4bd91954907b9d92db27199a3.1626608375.git.mchehab+huawei@kernel.org \
--to=mchehab+huawei@kernel.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=mauro.chehab@huawei.com \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).