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[2003:ea:8f2f:3200:ec8a:8637:bf5f:7faf]) by smtp.googlemail.com with ESMTPSA id o20sm243207712wrh.8.2019.08.08.13.01.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Aug 2019 13:01:44 -0700 (PDT) Subject: Re: [PATCH net] net: phy: rtl8211f: do a double read to get real time link status To: Andrew Lunn Cc: Yonglong Liu , davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linuxarm@huawei.com, salil.mehta@huawei.com, yisen.zhuang@huawei.com, shiju.jose@huawei.com References: <1565183772-44268-1-git-send-email-liuyonglong@huawei.com> <080b68c7-abe6-d142-da4b-26e8a7d4dc19@gmail.com> <20190808194049.GM27917@lunn.ch> From: Heiner Kallweit Message-ID: <26e2c5c9-915c-858b-d091-e5bfa7ab6a5b@gmail.com> Date: Thu, 8 Aug 2019 22:01:39 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190808194049.GM27917@lunn.ch> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08.08.2019 21:40, Andrew Lunn wrote: >> @@ -568,6 +568,11 @@ int phy_start_aneg(struct phy_device *phydev) >> if (err < 0) >> goto out_unlock; >> >> + /* The PHY may not yet have cleared aneg-completed and link-up bit >> + * w/o this delay when the following read is done. >> + */ >> + usleep_range(1000, 2000); >> + > > Hi Heiner > > Does 802.3 C22 say anything about this? > C22 says: "The Auto-Negotiation process shall be restarted by setting bit 0.9 to a logic one. This bit is self- clearing, and a PHY shall return a value of one in bit 0.9 until the Auto-Negotiation process has been initiated." Maybe we should read bit 0.9 in genphy_update_link() after having read BMSR and report aneg-complete and link-up as false (no matter of their current value) if 0.9 is set. > If this PHY is broken with respect to the standard, i would prefer the > workaround is in the PHY specific driver code, not generic core code. > Based on the C22 statement above the PHY may not be broken and the typical time between two MDIO accesses is sufficient for the PHY to clear the bits. I think of MDIO bus access functions in network chips that have a 10us-20us delay after each MDIO access. On HNS3 this may not be the case. > Andrew > Heiner