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Thu, 16 Jan 2020 15:52:41 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 22514100038; Thu, 16 Jan 2020 15:52:41 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag6node1.st.com [10.75.127.16]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0EEBC2FF5C9; Thu, 16 Jan 2020 15:52:41 +0100 (CET) Received: from lmecxl0923.lme.st.com (10.75.127.44) by SFHDAG6NODE1.st.com (10.75.127.16) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 Jan 2020 15:52:39 +0100 Subject: Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc To: Rob Herring CC: Ulf Hansson , Srinivas Kandagatla , Maxime Coquelin , Alexandre Torgue , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel@vger.kernel.org" , , linux-mmc , References: <20200110134823.14882-1-ludovic.barre@st.com> <20200110134823.14882-6-ludovic.barre@st.com> <20200115145645.GA599@bogus> <2ce63f11-8b0c-8261-63fa-cd19e874c537@st.com> From: Ludovic BARRE Message-ID: <27917fa9-e20f-02f3-d108-761632363347@st.com> Date: Thu, 16 Jan 2020 15:52:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: fr Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG6NODE1.st.com (10.75.127.16) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-01-16_04:2020-01-16,2020-01-15 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 1/16/20 à 3:33 PM, Rob Herring a écrit : > On Thu, Jan 16, 2020 at 3:21 AM Ludovic BARRE wrote: >> >> Hi Rob >> >> Le 1/15/20 à 3:56 PM, Rob Herring a écrit : >>> On Fri, Jan 10, 2020 at 02:48:19PM +0100, Ludovic Barre wrote: >>>> To support the sdr104 mode, the sdmmc variant has a >>>> hardware delay block to manage the clock phase when sampling >>>> data received by the card. >>>> >>>> This patch adds a second base register (optional) for >>>> sdmmc delay block. >>>> >>>> Signed-off-by: Ludovic Barre >>>> --- >>>> Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt >>>> index 6d3c626e017d..4ec921e4bf34 100644 >>>> --- a/Documentation/devicetree/bindings/mmc/mmci.txt >>>> +++ b/Documentation/devicetree/bindings/mmc/mmci.txt >>>> @@ -28,6 +28,8 @@ specific for ux500 variant: >>>> - st,sig-pin-fbclk : feedback clock signal pin used. >>>> >>>> specific for sdmmc variant: >>>> +- reg : a second base register may be defined if a delay >>>> + block is present and used for tuning. >>> >>> Which compatibles have a 2nd reg entry? >> >> In fact, mmci driver is ARM Amba driver (arm,primecell) and has only one >> compatible "arm,pl18x". >> The variants are identified by primecell-periphid property >> (discovered at runtime with HW block register or defined by >> device tree property "arm,primecell-periphid"). >> >> The defaults "arm,pl18x" variants have only one base register, >> but the SDMMC need a second base register for these >> delay block registers. >> >> example of sdmmc node: >> sdmmc1: sdmmc@58005000 { >> compatible = "arm,pl18x", "arm,primecell"; >> arm,primecell-periphid = <0x00253180>; >> reg = <0x58005000 0x1000>, <0x58006000 0x1000>; >> }; >> >> what do you advise? > > I missed that this is a primecell block. Just give some indication > which variants have this 2nd range. Thanks Rob. I will add primecell id(s) concerned by this 2nd range. > 0 > Rob >