From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: Martin Botka <martin.botka@somainline.org>, martin.botka1@gmail.com
Cc: ~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
Jami Kettunen <jamipkettunen@somainline.org>,
Paul Bouchara <paul.bouchara@somainline.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm6125: Add I2C and SPI nodes
Date: Sat, 1 Oct 2022 22:16:49 +0200 [thread overview]
Message-ID: <28cf6d46-23ee-51c6-53b8-3ff415d9c2a3@somainline.org> (raw)
In-Reply-To: <20221001185628.494884-2-martin.botka@somainline.org>
On 1.10.2022 20:56, Martin Botka wrote:
> This commit adds support for I2C and
> SPI on SM6125 SoC
>
> Signed-off-by: Martin Botka <martin.botka@somainline.org>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 296 +++++++++++++++++++++++++++
> 1 file changed, 296 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 350713742ccd..d35ea4474234 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -1076,6 +1076,302 @@ sdhc_2: mmc@4784000 {
> status = "disabled";
> };
>
> + qupv3_id_0: geniqup@4ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x04ac0000 0x2000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + i2c0: i2c@4a80000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a80000 0x4000>;
> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
#-cells at the end, before status.
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + dmas = <&gpi_dma0 0 0 3 64 0>,
> + <&gpi_dma0 1 0 3 64 0>;
Please use constants from <dt-bindings/dma/qcom-gpi.h>.
Konrad
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c0_default>;
> + pinctrl-1 = <&qup_i2c0_sleep>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@4a84000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a84000 0x4000>;
> + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + dmas = <&gpi_dma0 0 1 3 64 0>,
> + <&gpi_dma0 1 1 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c1_default>;
> + pinctrl-1 = <&qup_i2c1_sleep>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@4a88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a88000 0x4000>;
> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + dmas = <&gpi_dma0 0 2 3 64 0>,
> + <&gpi_dma0 1 2 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c2_default>;
> + pinctrl-1 = <&qup_i2c2_sleep>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@4a8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a8c000 0x4000>;
> + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + dmas = <&gpi_dma0 0 3 3 64 0>,
> + <&gpi_dma0 1 3 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c3_default>;
> + pinctrl-1 = <&qup_i2c3_sleep>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@4a90000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a90000 0x4000>;
> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + dmas = <&gpi_dma0 0 4 3 64 0>,
> + <&gpi_dma0 1 4 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c4_default>;
> + pinctrl-1 = <&qup_i2c4_sleep>;
> + status = "disabled";
> + };
> +
> + spi0: spi@4a80000 {
> + compatible = "qcom,geni-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x04a80000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_spi0_default>;
> + pinctrl-1 = <&qup_spi0_sleep>;
> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 0 1 64 0>,
> + <&gpi_dma0 1 0 1 64 0>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi2: spi@4a88000 {
> + compatible = "qcom,geni-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x04a88000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_spi2_default>;
> + pinctrl-1 = <&qup_spi2_sleep>;
> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 2 1 64 0>,
> + <&gpi_dma0 1 2 1 64 0>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + qupv3_id_1: geniqup@4cc0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x04cc0000 0x2000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + i2c5: i2c@4c80000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04c80000 0x4000>;
> + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> + dmas = <&gpi_dma1 0 0 3 64 0>,
> + <&gpi_dma1 1 0 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c5_default>;
> + pinctrl-1 = <&qup_i2c5_sleep>;
> + status = "disabled";
> + };
> +
> + i2c6: i2c@4c84000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04c84000 0x4000>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> + dmas = <&gpi_dma1 0 1 3 64 0>,
> + <&gpi_dma1 1 1 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c6_default>;
> + pinctrl-1 = <&qup_i2c6_sleep>;
> + status = "disabled";
> + };
> +
> + i2c7: i2c@4c88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04c88000 0x4000>;
> + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + dmas = <&gpi_dma1 0 2 3 64 0>,
> + <&gpi_dma1 1 2 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c7_default>;
> + pinctrl-1 = <&qup_i2c7_sleep>;
> + status = "disabled";
> + };
> +
> + i2c8: i2c@4c8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04c8c000 0x4000>;
> + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + dmas = <&gpi_dma1 0 3 3 64 0>,
> + <&gpi_dma1 1 3 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c8_default>;
> + pinctrl-1 = <&qup_i2c8_sleep>;
> + status = "disabled";
> + };
> +
> + i2c9: i2c@4c90000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04c90000 0x4000>;
> + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> + dmas = <&gpi_dma1 0 4 3 64 0>,
> + <&gpi_dma1 1 4 3 64 0>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_i2c9_default>;
> + pinctrl-1 = <&qup_i2c9_sleep>;
> + status = "disabled";
> + };
> +
> + spi5: spi@4c80000 {
> + compatible = "qcom,geni-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x04c80000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_spi5_default>;
> + pinctrl-1 = <&qup_spi5_sleep>;
> + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma1 0 0 1 64 0>,
> + <&gpi_dma1 1 0 1 64 0>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi6: spi@4c84000 {
> + compatible = "qcom,geni-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x04c84000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_spi6_default>;
> + pinctrl-1 = <&qup_spi6_sleep>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma1 0 1 1 64 0>,
> + <&gpi_dma1 1 1 1 64 0>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi8: spi@4c8c000 {
> + compatible = "qcom,geni-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x04c8c000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_spi8_default>;
> + pinctrl-1 = <&qup_spi8_sleep>;
> + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma1 0 3 1 64 0>,
> + <&gpi_dma1 1 3 1 64 0>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi9: spi@4c90000 {
> + compatible = "qcom,geni-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x04c90000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&qup_spi9_default>;
> + pinctrl-1 = <&qup_spi9_sleep>;
> + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma1 0 4 1 64 0>,
> + <&gpi_dma1 1 4 1 64 0>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> usb3: usb@4ef8800 {
> compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
> reg = <0x04ef8800 0x400>;
next prev parent reply other threads:[~2022-10-01 20:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 18:56 [PATCH 1/2] arm64: dts: qcom: sm6125: Add i2c and SPI pin configuration Martin Botka
2022-10-01 18:56 ` [PATCH 2/2] arm64: dts: qcom: sm6125: Add I2C and SPI nodes Martin Botka
2022-10-01 20:16 ` Konrad Dybcio [this message]
2022-10-04 14:29 ` kernel test robot
2022-10-01 20:14 ` [PATCH 1/2] arm64: dts: qcom: sm6125: Add i2c and SPI pin configuration Konrad Dybcio
2022-10-02 8:12 ` Krzysztof Kozlowski
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