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Wed, 9 Jun 2021 16:54:43 +0000 Received: from [10.26.49.10] (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Jun 2021 16:54:40 +0000 Subject: Re: Query regarding the use of pcie-designware-plat.c file To: Bjorn Helgaas , Vidya Sagar CC: , , , , , , , Thierry Reding , Krishna Thota , , References: <20210609163010.GA2643779@bjorn-Precision-5520> From: Jon Hunter Message-ID: <2970bdf2-bef2-bdcb-6ee3-ac1181d97b78@nvidia.com> Date: Wed, 9 Jun 2021 17:54:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210609163010.GA2643779@bjorn-Precision-5520> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 75542ed0-9c67-4aaf-047e-08d92b6747d6 X-MS-TrafficTypeDiagnostic: DM8PR12MB5431: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2021 16:54:43.5390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75542ed0-9c67-4aaf-047e-08d92b6747d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5431 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/06/2021 17:30, Bjorn Helgaas wrote: > On Wed, Jun 09, 2021 at 12:52:37AM +0530, Vidya Sagar wrote: >> Hi, >> I would like to know what is the use of pcie-designware-plat.c file. This >> looks like a skeleton file and can't really work with any specific hardware >> as such. >> Some context for this mail thread is, if the config CONFIG_PCIE_DW_PLAT is >> enabled in a system where a Synopsys DesignWare IP based PCIe controller is >> present and its configuration is enabled (Ex:- Tegra194 system with >> CONFIG_PCIE_TEGRA194_HOST enabled), then, it can so happen that the probe of >> pcie-designware-plat.c called first (because all DWC based PCIe controller >> nodes have "snps,dw-pcie" compatibility string) and can crash the system. > > What's the crash? If a device claims to be compatible with > "snps,dw-pcie" and pcie-designware-plat.c claims to know how to > operate "snps,dw-pcie" devices, it seems like something is wrong. > > "snps,dw-pcie" is a generic device type, so pcie-designware-plat.c > might not know how to operate device-specific details of some of those > devices, but basic functionality should work and it certainly > shouldn't crash. It is not really a crash but a hang when trying to access the hardware before it has been properly initialised. The scenario I saw was that if the Tegra194 PCIe driver was built as a module but the pcie-designware-plat.c was built into the kernel, then on boot we would attempt to probe the pcie-designware-plat.c driver because module was not available yet and this would hang. Hence, I removed the "snps,dw-pcie" compatible string for Tegra194 to avoid this and ONLY probe the Tegra194 PCIe driver. Sagar is wondering why this hang is only seen/reported for Tegra and could this happen to other platforms? I think that is potentially could. Jon -- nvpublic