From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 936B9C433DB for ; Wed, 3 Mar 2021 18:40:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 61EA264EEF for ; Wed, 3 Mar 2021 18:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1576000AbhCCRrS convert rfc822-to-8bit (ORCPT ); Wed, 3 Mar 2021 12:47:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234148AbhCCOkf (ORCPT ); Wed, 3 Mar 2021 09:40:35 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4178C0611C2 for ; Wed, 3 Mar 2021 06:39:39 -0800 (PST) Received: from lupine.hi.pengutronix.de ([2001:67c:670:100:3ad5:47ff:feaf:1a17] helo=lupine) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lHSez-0003rD-RS; Wed, 03 Mar 2021 15:39:33 +0100 Received: from pza by lupine with local (Exim 4.92) (envelope-from ) id 1lHSey-0000i4-TA; Wed, 03 Mar 2021 15:39:32 +0100 Message-ID: <29bf66f4b531ec701e85c23a411e40e3621b0ff8.camel@pengutronix.de> Subject: Re: [PATCH v3 4/5] media: hantro: Use reset driver From: Philipp Zabel To: Benjamin Gaignard , robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org, kernel@collabora.com Date: Wed, 03 Mar 2021 15:39:32 +0100 In-Reply-To: <20210301151754.104749-5-benjamin.gaignard@collabora.com> References: <20210301151754.104749-1-benjamin.gaignard@collabora.com> <20210301151754.104749-5-benjamin.gaignard@collabora.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote: > Rather use a reset like feature inside the driver use the reset > controller API to get the same result. > > Signed-off-by: Benjamin Gaignard > --- > drivers/staging/media/hantro/Kconfig | 1 + > drivers/staging/media/hantro/imx8m_vpu_hw.c | 61 ++++----------------- > 2 files changed, 12 insertions(+), 50 deletions(-) > > diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig > index 5b6cf9f62b1a..dd1d4dde2658 100644 > --- a/drivers/staging/media/hantro/Kconfig > +++ b/drivers/staging/media/hantro/Kconfig > @@ -20,6 +20,7 @@ config VIDEO_HANTRO_IMX8M > bool "Hantro VPU i.MX8M support" > depends on VIDEO_HANTRO > depends on ARCH_MXC || COMPILE_TEST > + select RESET_VPU_IMX8MQ > default y > help > Enable support for i.MX8M SoCs. > diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c > index c222de075ef4..d5b4312b9391 100644 > --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c > +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c > @@ -7,49 +7,12 @@ > > #include > #include > +#include > > #include "hantro.h" > #include "hantro_jpeg.h" > #include "hantro_g1_regs.h" > > -#define CTRL_SOFT_RESET 0x00 > -#define RESET_G1 BIT(1) > -#define RESET_G2 BIT(0) > - > -#define CTRL_CLOCK_ENABLE 0x04 > -#define CLOCK_G1 BIT(1) > -#define CLOCK_G2 BIT(0) > - > -#define CTRL_G1_DEC_FUSE 0x08 > -#define CTRL_G1_PP_FUSE 0x0c > -#define CTRL_G2_DEC_FUSE 0x10 > - > -static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) > -{ > - u32 val; > - > - /* Assert */ > - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); > - val &= ~reset_bits; > - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); > - > - udelay(2); > - > - /* Release */ > - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); > - val |= reset_bits; > - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); > -} > - > -static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) > -{ > - u32 val; > - > - val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); > - val |= clock_bits; > - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); The way it is implemented in the reset driver, the clocks are now ungated between assert and deassert instead of afterwards. Is this on purpose? regards Philipp