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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id c24sm537891lfc.155.2021.10.29.01.04.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Oct 2021 01:04:47 -0700 (PDT) Subject: Re: [PATCH 3/7] watchdog: s3c2410: Make reset disable optional To: Guenter Roeck , Sam Protsenko , Wim Van Sebroeck , Rob Herring Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org References: <20211028183527.3050-1-semen.protsenko@linaro.org> <20211028183527.3050-4-semen.protsenko@linaro.org> From: Krzysztof Kozlowski Message-ID: <2a5ff8d0-c665-e25e-cb40-51326db2e26a@canonical.com> Date: Fri, 29 Oct 2021 10:04:47 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/10/2021 02:16, Guenter Roeck wrote: > On 10/28/21 11:35 AM, Sam Protsenko wrote: >> Not all SoCs have AUTOMATIC_WDT_RESET_DISABLE register, examples are >> Exynos850 and Exynos9. On such chips reset disable register shouldn't be >> accessed. Provide a way to avoid handling that register. This is done by >> introducing separate callbacks to driver data structure: one for reset >> disable register, and one for mask reset register. Now those callbacks >> can be checked and called only when those were set in driver data. >> >> This commit doesn't bring any functional change to existing devices, but >> merely provides an infrastructure for upcoming chips support. >> > > That doesn't explain why the callbacks are needed instead of additional > feature flags. > Or why not skipping the disable operations if disable_reg is not provided? Best regards, Krzysztof