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[77.130.112.4]) by smtp.googlemail.com with ESMTPSA id d6sm12065156wrp.9.2019.04.15.05.16.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 05:16:50 -0700 (PDT) Subject: Re: [PATCH 7/7] clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Russell King , Will Deacon , Catalin Marinas , Mark Rutland , Wim Van Sebroeck , Guenter Roeck , Valentin Schneider References: <20190408154907.223536-1-marc.zyngier@arm.com> <20190408154907.223536-8-marc.zyngier@arm.com> From: Daniel Lezcano Message-ID: <2a60a031-1eab-2d5e-89ff-b5d516545eeb@linaro.org> Date: Mon, 15 Apr 2019 14:16:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190408154907.223536-8-marc.zyngier@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/04/2019 17:49, Marc Zyngier wrote: > Instead of always going via arch_counter_get_cntvct_stable to > access the counter workaround, let's have arch_timer_read_counter > to point to the right method. > > For that, we need to track whether any CPU in the system has a > workaround for the counter. This is done by having an atomic > variable tracking this. > > Signed-off-by: Marc Zyngier > --- [ ... ] > + > /* > * Default to cp15 based access because arm64 uses this function for > * sched_clock() before DT is probed and the cp15 method is guaranteed > @@ -372,6 +392,7 @@ static u32 notrace sun50i_a64_read_cntv_tval_el0(void) > DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); > EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); > > +static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0); Wouldn't make sense to READ_ONCE / WRITE_ONCE instead of using an atomic? > static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, > struct clock_event_device *clk) > @@ -550,6 +571,9 @@ void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa > per_cpu(timer_unstable_counter_workaround, i) = wa; > } > > + if (wa->read_cntvct_el0 || wa->read_cntpct_el0) > + atomic_set(&timer_unstable_counter_workaround_in_use, 1); > + [ ... ] -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog