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Thu, 28 May 2020 10:44:02 -0700 Subject: Re: [PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags To: Stephen Boyd , Jolly Shah , arm@kernel.org, linux-clk@vger.kernel.org, michal.simek@xilinx.com, mturquette@baylibre.com, olof@lixom.net Cc: rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tejas Patel , Rajan Vaja References: <1584048699-24186-1-git-send-email-jolly.shah@xilinx.com> <1584048699-24186-3-git-send-email-jolly.shah@xilinx.com> <159054169658.88029.371843532116000844@swboyd.mtv.corp.google.com> From: Jolly Shah Message-ID: <2c8cd31a-46ba-ec6a-67a7-f3d9abe561ff@xilinx.com> Date: Thu, 28 May 2020 10:44:01 -0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <159054169658.88029.371843532116000844@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(376002)(396003)(136003)(39860400002)(346002)(46966005)(9786002)(336012)(44832011)(426003)(54906003)(83380400001)(26005)(8676002)(110136005)(31686004)(15650500001)(8936002)(82740400003)(356005)(2906002)(82310400002)(478600001)(186003)(31696002)(53546011)(47076004)(2616005)(107886003)(81166007)(70206006)(36756003)(5660300002)(70586007)(316002)(4326008)(43740500002);DIR:OUT;SFP:1101; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 449b2bf3-329d-4644-f6f0-08d8032ebbab X-MS-TrafficTypeDiagnostic: BY5PR02MB6738: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 0417A3FFD2 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QUyWsHSu4nAAwSQR+g4f2CRNGF36g/tcf3eZkd2MLg8kBfBMEX38AZo55PkpLL08K8AiNS10V0WcA7yRTFYvP3urMCXljXi51ICVyS9t2sZdTd8sstqwj7Li7fJ1WUMdyKfYUx2tprSTqpXc3XnhLSTAoaCh0ngm6TskNWwrJ8/UylVTSdD/iTM/He23Uyt2w8JyivEhe+ZUI2zwKOe5E41HxYh6ZRpwf8QrUqzAD7zp21g87Ty5lD4jHUR4f3pR3uWUjMeh8PTv/v844z3kHTdYBw8Q4Q0tXzCWH6OVmUMD8TovWI6wFGVtiv58Ud14oRzdQ9Ns614cWDmXheOhY021r4UdSsg+j9t4/rMXVQI6o9KVIQYt5lwGQgLKt89spL0rfuy9NuOwA0LNT1LwOaoje4H7HMtJA3w3lPQtHLrLi/667/C768sQ5J556KJc X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2020 17:44:12.4793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 449b2bf3-329d-4644-f6f0-08d8032ebbab X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6738 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephan, Thanks for the review. > ------Original Message------ > From: Stephen Boyd > Sent: Tuesday, May 26, 2020 6:08PM > To: Jolly Shah , Arm , Linux-clk , Michal Simek , Mturquette , Olof > Cc: Rajan Vaja , Linux-arm-kernel@lists.infradead.org , Linux-kernel@vger.kernel.org , Tejas Patel , Rajan Vaja , Jolly Shah > Subject: Re: [PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags > > Quoting Jolly Shah (2020-03-12 14:31:39) >> From: Tejas Patel >> >> Older firmware version sets BIT(13) in clkflag to mark a >> divider as fractional divider. Updated firmware version sets BIT(4) >> in type flags to mark a divider as fractional divider since >> BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk >> framework flags. >> >> To support both old and new firmware version, consider BIT(13) from >> clkflag and BIT(4) from type_flag to check if divider is fractional >> or not. >> >> To maintain compatibility BIT(13) of clkflag in firmware will not be >> used in future for any purpose and will be marked as unused. > > Why are we mixing the firmware flags with the ccf flags? They shouldn't > be the same. The firmware should have its own 'flag numberspace' that is > distinct from the common clk framework's 'flag numberspace'. Please fix > the code. > Yes firmware flags are using separate numberspace now. Firmware maintains CCF and firmware specific flags separately but earlier CLK_FRAC was mistakenly defined in ccf flagspace and hence handled here for backward compatibility. Driver takes care of not registering same with CCF. Let me know if I misunderstood. Thanks, Jolly Shah