From: "Chocron, Jonathan" <jonnyc@amazon.com>
To: "helgaas@kernel.org" <helgaas@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"Woodhouse, David" <dwmw@amazon.co.uk>,
"Hanoch, Uri" <hanochu@amazon.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"Wasserstrom, Barak" <barakw@amazon.com>,
"Saidi, Ali" <alisaidi@amazon.com>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"Hawa, Hanna" <hhhawa@amazon.com>,
"Shenhar, Talel" <talel@amazon.com>,
"Krupnik, Ronen" <ronenk@amazon.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>
Subject: Re: [PATCH 4/8] PCI: Add quirk to disable MSI support for Amazon's Annapurna Labs host bridge
Date: Sun, 14 Jul 2019 15:09:28 +0000 [thread overview]
Message-ID: <2cac43401f0cf76acb645b98c6543204f12d5c05.camel@amazon.com> (raw)
In-Reply-To: <20190712130419.GA46935@google.com>
On Fri, 2019-07-12 at 08:04 -0500, Bjorn Helgaas wrote:
> On Thu, Jul 11, 2019 at 05:56:25PM +0300, Jonathan Chocron wrote:
> > On some platforms, the host bridge exposes an MSI-X capability but
> > doesn't actually support it.
> > This causes a crash during initialization by the pcieport driver,
> > since
> > it tries to configure the MSI-X capability.
>
> Nit: The formatting above is jarring to read because I can't tell
> whether it's one paragraph or two.
>
> Either rewrap it into a single paragraph or add a blank line to make
> two paragraphs. I noticed this elsewhere, too, in a comment, I
> think.
>
Ack.
> s/host bridge/Root Port/, if I understand correctly.
>
Ack.
BTW, what is the main difference between the 2 terms, since they seem
to be (mistakenly?) used interchangeably?
> I don't understand the "on some platforms..." part. Do you mean that
> on *every* platform, this particular host bridge (identified by
> [1c36:0031]) advertises an MSI-X capability that doesn't work?
>
> Or are there some platforms that configure the bridge so it doesn't
> advertise MSI-X at all, while other platforms configure it so it
> *does* advertise MSI-X?
>
The MSI-x capability isn't supported for this specific host bridge
([1c36:0031]). On some platforms, it is configured to not advertise the
capability at all, while on others it (mistakenly) does advertise it.
I've updated the commit message to be more explicit.
> If there's a line or two of diagnostics from the crash you could
> include here, that would help people who encounter the crash find
> the solution.
>
Sure, I'll add a partial stacktrace (a bit more than a couple of lines,
but I feel it will be too ambiguous otherwise).
> > Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> > ---
> > drivers/pci/quirks.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 11850b030637..0fb70d755977 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -2925,6 +2925,14 @@
> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
> > quirk_msi_intx_disable_qca_bug);
> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
> > quirk_msi_intx_disable_qca_bug);
> > +
> > +static void quirk_al_msi_disable(struct pci_dev *dev)
> > +{
> > + dev->no_msi = 1;
> > + dev_warn(&dev->dev, "Annapurna Labs pcie quirk - disabling
> > MSI\n");
>
> s/pcie/PCIe/ in English text, comments, printk strings, etc.
>
Ack.
> Actually, I think the whole "Annapurna Labs pcie quirk" part is
> probably unnecessary, since we can identify the device via the
> dev_printk() info.
>
Ack.
> Speaking of which, you can use "pci_warn(dev)" here to be consistent
> with the rest of the file.
>
Ack.
> > +}
> > +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS,
> > 0x0031,
> > + PCI_CLASS_BRIDGE_PCI, 8,
> > quirk_al_msi_disable);
>
> Why do you use the class fixup here instead of the simpler
> DECLARE_PCI_FIXUP_FINAL()? Requiring the class to match
> PCI_CLASS_BRIDGE_PCI suggests that there may be other [1c36:0031]
> devices that are not Root Ports. If that's the case, please mention
> it so it's clear why we need DECLARE_PCI_FIXUP_CLASS_FINAL(). If
> not,
> just use DECLARE_PCI_FIXUP_FINAL().
>
This is indeed the case. What do you say about adding the following
comment before the function's definition:
/*
* Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so
it
* should be disabled on platforms where the device (mistakenly)
advertises it.
*
* The 0031 device id is reused for other non Root Port device types,
* therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class
only.
*/
> #endif /* CONFIG_PCI_MSI */
/*
--
2.17.1
next prev parent reply other threads:[~2019-07-14 15:09 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-11 14:50 [PATCH 0/8] Amazon's Annapurna Labs DT-based PCIe host controller driver Jonathan Chocron
2019-07-11 14:45 ` [PATCH 5/8] dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding Jonathan Chocron
2019-07-11 7:12 ` Shenhar, Talel
2019-07-11 9:32 ` Lorenzo Pieralisi
2019-07-11 15:44 ` Chocron, Jonathan
2019-07-11 14:53 ` [PATCH 1/8] PCI: Add Amazon's Annapurna Labs vendor ID Jonathan Chocron
2019-07-12 13:04 ` Bjorn Helgaas
2019-07-11 14:55 ` [PATCH 2/8] PCI: Add ACS quirk for Amazon Annapurna Labs root ports Jonathan Chocron
2019-07-11 14:55 ` [PATCH 3/8] PCI/VPD: Add VPD release quirk for Amazon Annapurna Labs host bridge Jonathan Chocron
2019-07-12 13:10 ` Bjorn Helgaas
2019-07-14 15:08 ` Chocron, Jonathan
2019-07-11 14:56 ` [PATCH 4/8] PCI: Add quirk to disable MSI support for Amazon's " Jonathan Chocron
2019-07-12 13:04 ` Bjorn Helgaas
2019-07-14 15:09 ` Chocron, Jonathan [this message]
2019-07-14 22:54 ` Benjamin Herrenschmidt
2019-07-11 14:57 ` [PATCH 6/8] PCI: al: Add support for DW based driver type Jonathan Chocron
2019-07-12 13:42 ` Bjorn Helgaas
2019-07-15 15:18 ` Chocron, Jonathan
2019-07-11 14:57 ` [PATCH 7/8] PCI: dw: Add validation that PCIe core is set to correct mode Jonathan Chocron
2019-07-11 14:57 ` [PATCH 8/8] PCI: dw: Add support for PCI_PROBE_ONLY/PCI_REASSIGN_ALL_BUS flags Jonathan Chocron
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2cac43401f0cf76acb645b98c6543204f12d5c05.camel@amazon.com \
--to=jonnyc@amazon.com \
--cc=alisaidi@amazon.com \
--cc=barakw@amazon.com \
--cc=benh@kernel.crashing.org \
--cc=devicetree@vger.kernel.org \
--cc=dwmw@amazon.co.uk \
--cc=gustavo.pimentel@synopsys.com \
--cc=hanochu@amazon.com \
--cc=helgaas@kernel.org \
--cc=hhhawa@amazon.com \
--cc=jingoohan1@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=ronenk@amazon.com \
--cc=talel@amazon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).