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Thu, 5 Aug 2021 22:49:07 -0700 Envelope-to: git@xilinx.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, robh+dt@kernel.org, bgolaszewski@baylibre.com, iwamatsu@nigauri.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, zou_wei@huawei.com, arnd@arndb.de Received: from [172.30.17.109] (port=46834) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mBsjB-000Duj-Qa; Thu, 05 Aug 2021 22:49:06 -0700 Subject: Re: [PATCH V2 1/3] firmware: zynqmp: Add MMIO read and write support for PS_MODE pin To: Piyush Mehta , , , , , , , , , , CC: , , , , , References: <20210805174219.3000667-1-piyush.mehta@xilinx.com> <20210805174219.3000667-2-piyush.mehta@xilinx.com> From: Michal Simek Message-ID: <2cef2e97-18f8-9765-2600-27aa219fb2b2@xilinx.com> Date: Fri, 6 Aug 2021 07:49:02 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <20210805174219.3000667-2-piyush.mehta@xilinx.com> Content-Type: text/plain; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2021 05:49:08.2199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bdedfad-8d81-4e8e-8459-08d9589de87a X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6773 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/5/21 7:42 PM, Piyush Mehta wrote: > Add Xilinx ZynqMP firmware MMIO APIs support to set and get PS_MODE > pins value and status. These APIs create an interface path between > mode pin controller driver and low-level API to access GPIO pins. > > Signed-off-by: Piyush Mehta > --- > Changes in v2: > - Added Xilinx ZynqMP firmware MMIO API support to set and get pin > value and status. > --- > drivers/firmware/xilinx/zynqmp.c | 46 ++++++++++++++++++++++++++++++++++++ > include/linux/firmware/xlnx-zynqmp.h | 14 +++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c > index 15b13832..0234423 100644 > --- a/drivers/firmware/xilinx/zynqmp.c > +++ b/drivers/firmware/xilinx/zynqmp.c > @@ -28,6 +28,13 @@ > /* Max HashMap Order for PM API feature check (1<<7 = 128) */ > #define PM_API_FEATURE_CHECK_MAX_ORDER 7 > > +/* CRL registers and bitfields */ > +#define CRL_APB_BASE 0xFF5E0000U > +/* BOOT_PIN_CTRL- Used to control the mode pins after boot */ > +#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + (0x250U)) > +/* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */ > +#define CRL_APB_BOOTPIN_CTRL_MASK 0xF0FU > + > static bool feature_check_enabled; > static DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER); > > @@ -926,6 +933,45 @@ int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, > EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config); > > /** > + * zynqmp_pm_bootmode_read() - PM Config API for read bootpin status > + * @ps_mode: Returned output value of ps_mode > + * > + * This API function is to be used for notify the power management controller > + * to read bootpin status. > + * > + * Return: status, either success or error+reason > + */ > +unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) > +{ > + unsigned int ret; > + u32 ret_payload[PAYLOAD_ARG_CNT]; > + > + ret = zynqmp_pm_invoke_fn(PM_MMIO_READ, CRL_APB_BOOT_PIN_CTRL, 0, > + 0, 0, ret_payload); > + > + *ps_mode = ret_payload[1]; > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_read); > + > +/** > + * zynqmp_pm_bootmode_write() - PM Config API for Configure bootpin > + * @ps_mode: Value to be written to the bootpin ctrl register > + * > + * This API function is to be used for notify the power management controller > + * to configure bootpin. > + * > + * Return: Returns status, either success or error+reason > + */ > +int zynqmp_pm_bootmode_write(u32 ps_mode) > +{ > + return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, CRL_APB_BOOT_PIN_CTRL, > + CRL_APB_BOOTPIN_CTRL_MASK, ps_mode, 0, NULL); > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_write); > + > +/** > * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller > * master has initialized its own power management > * > diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h > index 9d1a5c1..dc6f39f 100644 > --- a/include/linux/firmware/xlnx-zynqmp.h > +++ b/include/linux/firmware/xlnx-zynqmp.h > @@ -68,6 +68,8 @@ enum pm_api_id { > PM_SET_REQUIREMENT = 15, > PM_RESET_ASSERT = 17, > PM_RESET_GET_STATUS = 18, > + PM_MMIO_WRITE = 19, > + PM_MMIO_READ = 20, > PM_PM_INIT_FINALIZE = 21, > PM_FPGA_LOAD = 22, > PM_FPGA_GET_STATUS = 23, > @@ -386,6 +388,8 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); > int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, > const enum zynqmp_pm_reset_action assert_flag); > int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); > +unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode); > +int zynqmp_pm_bootmode_write(u32 ps_mode); > int zynqmp_pm_init_finalize(void); > int zynqmp_pm_set_suspend_mode(u32 mode); > int zynqmp_pm_request_node(const u32 node, const u32 capabilities, > @@ -515,6 +519,16 @@ static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, > return -ENODEV; > } > > +static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) > +{ > + return -ENODEV; > +} > + > +static inline int zynqmp_pm_bootmode_write(u32 ps_mode) > +{ > + return -ENODEV; > +} > + > static inline int zynqmp_pm_init_finalize(void) > { > return -ENODEV; > Acked-by: Michal Simek Thanks, Michal