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From: Johan Jonker <jbx6244@gmail.com>
To: Benjamin Gaignard <benjamin.gaignard@collabora.com>,
	kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org,
	heiko@sntech.de, pgwipeout@gmail.com
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	kernel@collabora.com
Subject: Re: [PATCH 2/4] dt-bindings: phy: rockchip: USB2: Add compatible for rk3568
Date: Mon, 14 Jun 2021 20:19:22 +0200	[thread overview]
Message-ID: <2d1e35d1-92ab-7ca2-d2e7-13b3885adaa9@gmail.com> (raw)
In-Reply-To: <20210614154359.805555-3-benjamin.gaignard@collabora.com>

Hi Benjamin,

The '#phy-cells' in [PATCH 1/4] are already gone.
The nodename is renamed to pattern "usb2phy@[0-9a-f]+$".
phy-rockchip-inno-usb2.yaml is now also part of grf.yaml, so must take
care of both.

From rk3568.dtsi:

	usb2phy0_grf: syscon@fdca0000 {
		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
		reg = <0x0 0xfdca0000 0x0 0x8000>;
	};

	usb2phy1_grf: syscon@fdca8000 {
		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
		reg = <0x0 0xfdca8000 0x0 0x8000>;
	};

	usb2phy0: usb2phy@fe8a0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x0 0xfe8a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru CLK_USBPHY0_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		assigned-clocks = <&cru USB480M>;
		assigned-clock-parents = <&usb2phy0>;
		clock-output-names = "usb480m_phy";
		rockchip,usbgrf = <&usb2phy0_grf>;
		status = "disabled";

		u2phy0_host: host-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		u2phy0_otg: otg-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};

	usb2phy1: usb2phy@fe8b0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x0 0xfe8b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru CLK_USBPHY1_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		rockchip,usbgrf = <&usb2phy1_grf>;
		status = "disabled";

		u2phy1_host: host-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		u2phy1_otg: otg-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};

rockchip,rk3568-usb2phy-grf must also be added to grf.yaml.

See linux-next.

https://lore.kernel.org/linux-devicetree/20210601164800.7670-2-jbx6244@gmail.com/

Johan

On 6/14/21 5:43 PM, Benjamin Gaignard wrote:
> Add "rockchip,rk3568-usb2phy" in compatible list of the USB2 phy.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> ---
>  .../devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml          | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> index b14387a48f6a3..a1420d5e44be7 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> @@ -18,6 +18,7 @@ properties:
>        - rockchip,rk3366-usb2phy
>        - rockchip,rk3399-usb2phy

--->

>        - rockchip,rv1108-usb2phy

> +      - rockchip,rk3568-usb2phy

Please sort in alphabetical order.

>  
>    reg:
>      maxItems: 1
> 

  reply	other threads:[~2021-06-14 18:20 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-14 15:43 [PATCH 0/4] Add USB2 support for rk3568 Benjamin Gaignard
2021-06-14 15:43 ` [PATCH 1/4] dt-bindings: phy: rockchip: USB2: remove useless #phy-cells property Benjamin Gaignard
2021-06-15 14:04   ` Rob Herring
2021-06-15 22:51   ` Rob Herring
2021-06-14 15:43 ` [PATCH 2/4] dt-bindings: phy: rockchip: USB2: Add compatible for rk3568 Benjamin Gaignard
2021-06-14 18:19   ` Johan Jonker [this message]
2021-06-14 15:43 ` [PATCH 3/4] PHY: rockchip: USB2: Allow 64 bits reg property Benjamin Gaignard
2021-06-14 17:09   ` Robin Murphy
2021-06-14 21:58     ` Peter Geis
2021-06-14 15:43 ` [PATCH 4/4] phy: rockchip: USB2: Add support for rk3568 Benjamin Gaignard
2021-06-14 16:33 ` [PATCH 0/4] Add USB2 " Peter Geis

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