From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AF87C432BE for ; Fri, 23 Jul 2021 11:54:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 480FB60E8C for ; Fri, 23 Jul 2021 11:54:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234629AbhGWLNu (ORCPT ); Fri, 23 Jul 2021 07:13:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:42570 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234255AbhGWLNr (ORCPT ); Fri, 23 Jul 2021 07:13:47 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8929660E8C; Fri, 23 Jul 2021 11:54:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627041260; bh=EEKAfL+ekTyTA9+l9YOuImum0F+5Sz5mkjHlOyhrl/s=; h=From:To:Cc:Subject:Date:From; b=WjCXAIP8q3AgFIEfCbp7qJl+AejObU1jZuKEnJQ+mWYKMV8v/cMhQmEd5prObZKpZ GB0TIYPnRdZ6yfYaWfsV6PH63eW6ZyM8EUieTwsft28koewKsz1/rQIqUrEx1lrfrS meJ0uvZeWJbem6W9HuBkw2VdX0LzD1GYacJJcRFiBjWaLqe+29BBaOu5btFmeKqpLE Cix5VbV0/gp92AXKRvn3ALJUikzF8tXDMR4s0tPqU3oqKca6jpQjjTQXJcBdo0aahX JWq/SpgV5T5lDp8rDgYUBEKPSRCdNYq456BK4Y/ZSqTkQa8bNzIxTMCnRUDnx+pXkT 7KLJ/hEJPaOXg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m6tkw-00ALqj-5G; Fri, 23 Jul 2021 13:54:18 +0200 From: Mauro Carvalho Chehab To: Michael Turquette , Stephen Boyd Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: clk-hi3670: Add CLK_IGNORE_UNUSED flag Date: Fri, 23 Jul 2021 13:54:16 +0200 Message-Id: <2d2de5e902ced072bcfd5e5311d6b10326b9245b.1627041240.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are several clocks that are required for Kirin 970 to work. Without them, the system hangs. However, most of the clocks defined at clk-hi3670 aren't specified on its device tree, nor at Hikey 970 one. A few of them are defined at the Linaro's official tree for Hikey 970, but, even on the official tree for HiKey 970 distros use: clk_ignore_unused=true as a boot option, as otherwise the system will hang in ~2 seconds, before even printing a prompt. That prevents a generic ARM64 Kernel to boot on such hardware. So, Modify the the driver to use CLK_IGNORE_UNUSED flags at the clock groups that are needed for the device to boot, in order to get rid of the need of a boot parameter. Signed-off-by: Mauro Carvalho Chehab --- drivers/clk/hisilicon/clk-hi3670.c | 355 ++++++++++++++++------------- 1 file changed, 193 insertions(+), 162 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c index 4d05a71683a5..cec53ff9f8fb 100644 --- a/drivers/clk/hisilicon/clk-hi3670.c +++ b/drivers/clk/hisilicon/clk-hi3670.c @@ -78,278 +78,306 @@ static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = { static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = { { HI3670_PPLL1_EN_ACPU, "ppll1_en_acpu", "clk_ppll1", - CLK_SET_RATE_PARENT, 0x0, 0, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 0, 0, }, { HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2", - CLK_SET_RATE_PARENT, 0x0, 3, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 3, 0, }, { HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3", - CLK_SET_RATE_PARENT, 0x0, 27, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 27, 0, }, { HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1", - CLK_SET_RATE_PARENT, 0x460, 16, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x460, 16, 0, }, { HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2", - CLK_SET_RATE_PARENT, 0x460, 18, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x460, 18, 0, }, { HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3", - CLK_SET_RATE_PARENT, 0x460, 20, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x460, 20, 0, }, { HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2", - CLK_SET_RATE_PARENT, 0x410, 27, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x410, 27, 0, }, { HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3", - CLK_SET_RATE_PARENT, 0x410, 28, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x410, 28, 0, }, { HI3670_CLK_GATE_PPLL4_MEDIA, "clk_gate_ppll4_media", "clk_ppll4", - CLK_SET_RATE_PARENT, 0x410, 26, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x410, 26, 0, }, { HI3670_CLK_GATE_PPLL6_MEDIA, "clk_gate_ppll6_media", "clk_ppll6", - CLK_SET_RATE_PARENT, 0x410, 30, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x410, 30, 0, }, { HI3670_CLK_GATE_PPLL7_MEDIA, "clk_gate_ppll7_media", "clk_ppll7", - CLK_SET_RATE_PARENT, 0x410, 29, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x410, 29, 0, }, { HI3670_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 0, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 0, 0, }, { HI3670_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 1, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 1, 0, }, { HI3670_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 2, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 2, 0, }, { HI3670_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 3, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 3, 0, }, { HI3670_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 4, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 4, 0, }, { HI3670_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 5, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 5, 0, }, { HI3670_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 6, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 6, 0, }, { HI3670_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 7, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 7, 0, }, { HI3670_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 8, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 8, 0, }, { HI3670_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 9, 0, }, { HI3670_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 10, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 10, 0, }, { HI3670_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 11, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 11, 0, }, { HI3670_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 12, 0, }, { HI3670_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 13, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 13, 0, }, { HI3670_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 14, 0, }, { HI3670_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 15, 0, }, { HI3670_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 16, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 16, 0, }, { HI3670_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 17, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 17, 0, }, { HI3670_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 20, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 20, 0, }, { HI3670_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x10, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 21, 0, }, { HI3670_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x50, 28, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x50, 28, 0, }, { HI3670_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus", - CLK_SET_RATE_PARENT, 0x50, 29, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x50, 29, 0, }, { HI3670_HCLK_GATE_USB3OTG, "hclk_gate_usb3otg", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x0, 25, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 25, 0, }, { HI3670_ACLK_GATE_USB3DVFS, "aclk_gate_usb3dvfs", "autodiv_emmc0bus", - CLK_SET_RATE_PARENT, 0x40, 1, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 1, 0, }, { HI3670_HCLK_GATE_SDIO, "hclk_gate_sdio", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x0, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 21, 0, }, { HI3670_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus", - CLK_SET_RATE_PARENT, 0x420, 7, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x420, 7, 0, }, { HI3670_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "pclk_gate_mmc1_pcie", - CLK_SET_RATE_PARENT, 0x420, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x420, 9, 0, }, { HI3670_PCLK_GATE_MMC1_PCIE, "pclk_gate_mmc1_pcie", "pclk_div_mmc1_pcie", - CLK_SET_RATE_PARENT, 0x30, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 12, 0, }, { HI3670_PCLK_GATE_MMC0_IOC, "pclk_gate_mmc0_ioc", "clk_div_mmc0bus", - CLK_SET_RATE_PARENT, 0x40, 13, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 13, 0, }, { HI3670_PCLK_GATE_MMC1_IOC, "pclk_gate_mmc1_ioc", "clk_div_mmc1bus", - CLK_SET_RATE_PARENT, 0x420, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x420, 21, 0, }, { HI3670_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x30, 1, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 1, 0, }, { HI3670_CLK_GATE_VCODECBUS2DDR, "clk_gate_vcodecbus2ddr", "clk_div_vcodecbus", - CLK_SET_RATE_PARENT, 0x0, 5, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 5, 0, }, { HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq", - CLK_SET_RATE_PARENT, 0x22C, 28, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x22C, 28, 0, }, { HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq", - CLK_SET_RATE_PARENT, 0x50, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x50, 14, 0, }, { HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys", - CLK_SET_RATE_PARENT, 0x40, 17, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 17, 0, }, { HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x0, 30, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 30, 0, }, { HI3670_CLK_GATE_SDIO, "clk_gate_sdio", "clk_mux_sdio_sys", - CLK_SET_RATE_PARENT, 0x40, 19, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 19, 0, }, { HI3670_CLK_GATE_A57HPM, "clk_gate_a57hpm", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x050, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x050, 9, 0, }, { HI3670_CLK_GATE_A53HPM, "clk_gate_a53hpm", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x050, 13, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x050, 13, 0, }, { HI3670_CLK_GATE_PA_A53, "clk_gate_pa_a53", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x480, 10, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x480, 10, 0, }, { HI3670_CLK_GATE_PA_A57, "clk_gate_pa_a57", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x480, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x480, 9, 0, }, { HI3670_CLK_GATE_PA_G3D, "clk_gate_pa_g3d", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x480, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x480, 15, 0, }, { HI3670_CLK_GATE_GPUHPM, "clk_gate_gpuhpm", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x050, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x050, 15, 0, }, { HI3670_CLK_GATE_PERIHPM, "clk_gate_perihpm", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x050, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x050, 12, 0, }, { HI3670_CLK_GATE_AOHPM, "clk_gate_aohpm", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x050, 11, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x050, 11, 0, }, { HI3670_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth", - CLK_SET_RATE_PARENT, 0x20, 11, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 11, 0, }, { HI3670_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth", - CLK_SET_RATE_PARENT, 0x20, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 14, 0, }, { HI3670_PCLK_GATE_UART1, "pclk_gate_uart1", "clk_mux_uarth", - CLK_SET_RATE_PARENT, 0x20, 11, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 11, 0, }, { HI3670_PCLK_GATE_UART4, "pclk_gate_uart4", "clk_mux_uarth", - CLK_SET_RATE_PARENT, 0x20, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 14, 0, }, { HI3670_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uartl", - CLK_SET_RATE_PARENT, 0x20, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 12, 0, }, { HI3670_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uartl", - CLK_SET_RATE_PARENT, 0x20, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 15, 0, }, { HI3670_PCLK_GATE_UART2, "pclk_gate_uart2", "clk_mux_uartl", - CLK_SET_RATE_PARENT, 0x20, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 12, 0, }, { HI3670_PCLK_GATE_UART5, "pclk_gate_uart5", "clk_mux_uartl", - CLK_SET_RATE_PARENT, 0x20, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 15, 0, }, { HI3670_CLK_GATE_UART0, "clk_gate_uart0", "clk_mux_uart0", - CLK_SET_RATE_PARENT, 0x20, 10, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 10, 0, }, { HI3670_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c", - CLK_SET_RATE_PARENT, 0x20, 7, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 7, 0, }, { HI3670_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c", - CLK_SET_RATE_PARENT, 0x20, 27, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 27, 0, }, { HI3670_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c", - CLK_SET_RATE_PARENT, 0x10, 31, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 31, 0, }, { HI3670_PCLK_GATE_I2C3, "pclk_gate_i2c3", "clk_mux_i2c", - CLK_SET_RATE_PARENT, 0x20, 7, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 7, 0, }, { HI3670_PCLK_GATE_I2C4, "pclk_gate_i2c4", "clk_mux_i2c", - CLK_SET_RATE_PARENT, 0x20, 27, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 27, 0, }, { HI3670_PCLK_GATE_I2C7, "pclk_gate_i2c7", "clk_mux_i2c", - CLK_SET_RATE_PARENT, 0x10, 31, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x10, 31, 0, }, { HI3670_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi", - CLK_SET_RATE_PARENT, 0x20, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 9, 0, }, { HI3670_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi", - CLK_SET_RATE_PARENT, 0x40, 4, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 4, 0, }, { HI3670_PCLK_GATE_SPI1, "pclk_gate_spi1", "clk_mux_spi", - CLK_SET_RATE_PARENT, 0x20, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 9, 0, }, { HI3670_PCLK_GATE_SPI4, "pclk_gate_spi4", "clk_mux_spi", - CLK_SET_RATE_PARENT, 0x40, 4, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 4, 0, }, { HI3670_CLK_GATE_USB3OTG_REF, "clk_gate_usb3otg_ref", "clkin_sys", - CLK_SET_RATE_PARENT, 0x40, 0, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 0, 0, }, { HI3670_CLK_GATE_USB2PHY_REF, "clk_gate_usb2phy_ref", "clkin_sys", - CLK_SET_RATE_PARENT, 0x410, 19, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x410, 19, 0, }, { HI3670_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys", - CLK_SET_RATE_PARENT, 0x420, 8, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x420, 8, 0, }, { HI3670_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_gate_mmc1_pcieaxi", - CLK_SET_RATE_PARENT, 0x420, 5, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x420, 5, 0, }, { HI3670_CLK_GATE_MMC1_PCIEAXI, "clk_gate_mmc1_pcieaxi", "clk_div_pcieaxi", - CLK_SET_RATE_PARENT, 0x050, 4, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x050, 4, 0, }, { HI3670_CLK_GATE_PCIEPHY_REF, "clk_gate_pciephy_ref", "clk_ppll_pcie", - CLK_SET_RATE_PARENT, 0x470, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x470, 14, 0, }, { HI3670_CLK_GATE_PCIE_DEBOUNCE, "clk_gate_pcie_debounce", "clk_ppll_pcie", - CLK_SET_RATE_PARENT, 0x470, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x470, 12, 0, }, { HI3670_CLK_GATE_PCIEIO, "clk_gate_pcieio", "clk_ppll_pcie", - CLK_SET_RATE_PARENT, 0x470, 13, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x470, 13, 0, }, { HI3670_CLK_GATE_PCIE_HP, "clk_gate_pcie_hp", "clk_ppll_pcie", - CLK_SET_RATE_PARENT, 0x470, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x470, 15, 0, }, { HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp", - CLK_SET_RATE_PARENT, 0x0, 26, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x0, 26, 0, }, { HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp", - CLK_SET_RATE_PARENT, 0x20, 31, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 31, 0, }, { HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans", - CLK_SET_RATE_PARENT, 0x30, 24, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 24, 0, }, { HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans", - CLK_SET_RATE_PARENT, 0x30, 25, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 25, 0, }, { HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp", - CLK_SET_RATE_PARENT, 0x20, 0, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x20, 0, 0, }, { HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192", - CLK_SET_RATE_PARENT, 0x30, 8, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 8, 0, }, { HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192", - CLK_SET_RATE_PARENT, 0x30, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 9, 0, }, { HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0", - CLK_SET_RATE_PARENT, 0x30, 19, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x30, 19, 0, }, { HI3670_ABB_AUDIO_GT_EN1, "abb_audio_gt_en1", "abb_audio_en1", - CLK_SET_RATE_PARENT, 0x40, 20, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 20, 0, }, { HI3670_CLK_GATE_DP_AUDIO_PLL_AO, "clk_gate_dp_audio_pll_ao", "clkdiv_dp_audio_pll_ao", - CLK_SET_RATE_PARENT, 0x00, 13, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x00, 13, 0, }, { HI3670_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys", - CLK_SET_RATE_PARENT, 0, 1, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0, 1, 0, }, { HI3670_PERI_VOLT_MIDDLE, "peri_volt_middle", "clkin_sys", - CLK_SET_RATE_PARENT, 0, 1, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0, 1, 0, }, { HI3670_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", "clk_isp_snclk_mux0", - CLK_SET_RATE_PARENT, 0x50, 16, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x50, 16, 0, }, { HI3670_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", "clk_isp_snclk_mux1", - CLK_SET_RATE_PARENT, 0x50, 17, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x50, 17, 0, }, { HI3670_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux2", - CLK_SET_RATE_PARENT, 0x50, 18, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x50, 18, 0, }, { HI3670_CLK_GATE_RXDPHY0_CFG, "clk_gate_rxdphy0_cfg", "clk_mux_rxdphy_cfg", - CLK_SET_RATE_PARENT, 0x030, 20, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 20, 0, }, { HI3670_CLK_GATE_RXDPHY1_CFG, "clk_gate_rxdphy1_cfg", "clk_mux_rxdphy_cfg", - CLK_SET_RATE_PARENT, 0x030, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 21, 0, }, { HI3670_CLK_GATE_RXDPHY2_CFG, "clk_gate_rxdphy2_cfg", "clk_mux_rxdphy_cfg", - CLK_SET_RATE_PARENT, 0x030, 22, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 22, 0, }, { HI3670_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys", - CLK_SET_RATE_PARENT, 0x030, 28, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 28, 0, }, { HI3670_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys", - CLK_SET_RATE_PARENT, 0x030, 29, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 29, 0, }, { HI3670_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys", - CLK_SET_RATE_PARENT, 0x030, 30, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 30, 0, }, { HI3670_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys", - CLK_SET_RATE_PARENT, 0x030, 31, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x030, 31, 0, }, { HI3670_CLK_GATE_MEDIA_TCXO, "clk_gate_media_tcxo", "clkin_sys", - CLK_SET_RATE_PARENT, 0x40, 6, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x40, 6, 0, }, }; static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = { { HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x404, 5, CLK_GATE_HIWORD_MASK, }, { HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus", - CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x404, 1, CLK_GATE_HIWORD_MASK, }, { HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m", - CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xf8, 13, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus", - CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x0F0, 8, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll", - CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 3, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys", - CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 5, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll", - CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 8, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys", - CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 6, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm", - CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x0F4, 7, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m", - CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF8, 10, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m", - CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 11, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m", - CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 10, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m", - CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 9, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m", - CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 13, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi", - CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xfc, 15, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp", - CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 4, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2", - CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 14, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2", - CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF4, 1, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m", - CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF8, 5, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0", - CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF0, 10, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0", - CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF0, 11, CLK_GATE_HIWORD_MASK, }, { HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6", - CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF8, 15, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec", - CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF0, 13, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc", - CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xF0, 9, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x108, 2, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm", - CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x0F0, 12, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics", - CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0xf0, 14, CLK_GATE_HIWORD_MASK, }, { HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus", - CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x404, 3, CLK_GATE_HIWORD_MASK, }, }; static const char *const @@ -555,65 +583,68 @@ static const struct hisi_gate_clock hi3670_pctrl_gate_clks[] = { /* clk_sctrl */ static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = { { HI3670_PPLL0_EN_ACPU, "ppll0_en_acpu", "clk_ppll0", - CLK_SET_RATE_PARENT, 0x190, 26, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x190, 26, 0, }, { HI3670_PPLL0_GT_CPU, "ppll0_gt_cpu", "clk_ppll0", - CLK_SET_RATE_PARENT, 0x190, 15, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x190, 15, 0, }, { HI3670_CLK_GATE_PPLL0_MEDIA, "clk_gate_ppll0_media", "clk_ppll0", - CLK_SET_RATE_PARENT, 0x1b0, 6, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1b0, 6, 0, }, { HI3670_PCLK_GPIO18, "pclk_gpio18", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x1B0, 9, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1B0, 9, 0, }, { HI3670_PCLK_GPIO19, "pclk_gpio19", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x1B0, 8, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1B0, 8, 0, }, { HI3670_CLK_GATE_SPI, "clk_gate_spi", "clk_div_ioperi", - CLK_SET_RATE_PARENT, 0x1B0, 10, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1B0, 10, 0, }, { HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi", - CLK_SET_RATE_PARENT, 0x1B0, 10, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1B0, 10, 0, }, { HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys", - CLK_SET_RATE_PARENT, 0x1B0, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1B0, 14, 0, }, { HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys", - CLK_SET_RATE_PARENT, 0x1b0, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1b0, 12, 0, }, { HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 11, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 11, 0, }, { HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 12, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 12, 0, }, { HI3670_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 13, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 13, 0, }, { HI3670_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 14, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 14, 0, }, { HI3670_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 21, 0, }, { HI3670_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 22, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 22, 0, }, { HI3670_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 25, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 25, 0, }, { HI3670_CLK_GATE_OUT0, "clk_gate_out0", "clk_mux_clkout0", - CLK_SET_RATE_PARENT, 0x160, 16, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 16, 0, }, { HI3670_CLK_GATE_OUT1, "clk_gate_out1", "clk_mux_clkout1", - CLK_SET_RATE_PARENT, 0x160, 17, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 17, 0, }, { HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus", - CLK_SET_RATE_PARENT, 0x160, 19, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 19, 0, }, { HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys", - CLK_SET_RATE_PARENT, 0x160, 20, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 20, 0, }, { HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri", "clk_mux_asp_subsys_peri", - CLK_SET_RATE_PARENT, 0x170, 6, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x170, 6, 0, }, { HI3670_CLK_GATE_ASP_SUBSYS, "clk_gate_asp_subsys", "clk_mux_asp_pll", - CLK_SET_RATE_PARENT, 0x170, 4, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x170, 4, 0, }, { HI3670_CLK_GATE_ASP_TCXO, "clk_gate_asp_tcxo", "clkin_sys", - CLK_SET_RATE_PARENT, 0x160, 27, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x160, 27, 0, }, { HI3670_CLK_GATE_DP_AUDIO_PLL, "clk_gate_dp_audio_pll", "clk_gate_dp_audio_pll_ao", - CLK_SET_RATE_PARENT, 0x1B0, 7, 0, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x1B0, 7, 0, }, }; static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = { { HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0", - CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x270, 6, CLK_GATE_HIWORD_MASK, }, { HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri", "clk_ppll0", - CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x268, 3, CLK_GATE_HIWORD_MASK, }, { HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0", - CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, }, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + 0x258, 0, CLK_GATE_HIWORD_MASK, }, }; static const char *const -- 2.31.1