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Wed, 5 May 2021 20:04:21 +0000 Subject: Re: [PATCH v4 2/2] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs To: Alex Williamson , Amey Narkhede CC: Oliver O'Halloran , Bjorn Helgaas , Bjorn Helgaas , linux-pci , Linux Kernel Mailing List , Sinan Kaya , Vikram Sethi References: <478efe56-fb64-6987-f64c-f3d930a3b330@nvidia.com> <20210505021236.GA1244944@bjorn-Precision-5520> <20210505174032.sursnpwkfrc5qji2@archlinux> <20210505131357.07e55042@redhat.com> From: Shanker R Donthineni Message-ID: <2e64d906-d398-a859-413a-c7ab3341de88@nvidia.com> Date: Wed, 5 May 2021 15:04:18 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210505131357.07e55042@redhat.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-US X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e0672493-dad1-495c-dcca-08d91000fa16 X-MS-TrafficTypeDiagnostic: DM6PR12MB4864: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2021 20:04:22.9723 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0672493-dad1-495c-dcca-08d91000fa16 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4864 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks Alex for the detailed explanation. On 5/5/21 2:13 PM, Alex Williamson wrote: > I'm also assuming all SoCs integrating this GPU will provide a > _RST method, but we're also disabling SBR in this series to avoid the > only other generic reset option we'd have for this device. All the platforms/SoCs which contain these GPUs will provide ACPI/firmware with _RST method.   > In the more general case, I'd expect that system firmware isn't going > to implement an _RST method for a pluggable slot, so we'll lookup the > ACPI handle, fail to find a _RST method and drop to the next option. > For a PCI/e slot, at best the _RST method might be included in the _PRR > scope rather than the device scope to indicate it affects the entire > slot. That could be something like the #PERST below or a warm reset. I > don't think we're enabling that here, are we? No, our_RST method will be included only in a device context (not _PRP).