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Wed, 28 Feb 2024 15:11:37 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41SFBaCK010479 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Feb 2024 15:11:36 GMT Received: from [10.216.14.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 28 Feb 2024 07:11:27 -0800 Message-ID: <2e8ff010-2129-55e0-55b7-5a1589d27798@quicinc.com> Date: Wed, 28 Feb 2024 20:41:22 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v7 3/7] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path Content-Language: en-US To: Bjorn Helgaas CC: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Rob Herring , Johan Hovold , Brian Masney , Georgi Djakov , , , , , , , , , , Bryan O'Donoghue References: <20240228145051.GA271533@bhelgaas> From: Krishna Chaitanya Chundru In-Reply-To: <20240228145051.GA271533@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: LitNJhq6cC_bjasrp6uvlpEFM25PtURf X-Proofpoint-GUID: LitNJhq6cC_bjasrp6uvlpEFM25PtURf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-28_07,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402280119 On 2/28/2024 8:20 PM, Bjorn Helgaas wrote: > On Wed, Feb 28, 2024 at 12:08:37PM +0530, Krishna Chaitanya Chundru wrote: >> On 2/28/2024 4:52 AM, Bjorn Helgaas wrote: >>> On Fri, Feb 23, 2024 at 08:18:00PM +0530, Krishna chaitanya chundru wrote: >>>> To access PCIe registers, PCIe BAR space, config space the CPU-PCIe >>>> ICC(interconnect consumers) path should be voted otherwise it may >>>> lead to NoC(Network on chip) timeout. We are surviving because of >>>> other driver vote for this path. >>>> As there is less access on this path compared to PCIe to mem path >>>> add minimum vote i.e 1KBps bandwidth always. > >>>> + * The config space, BAR space and registers goes through cpu-pcie path. >>>> + * Set peak bandwidth to 1KBps as recommended by HW team for this path all the time. >>> >>> Wrap to fit in 80 columns. > >> We have limit up to 100 columns in the driver right, I am ok to change to 80 >> but just checking if I misunderstood something. > > I should have said "wrap to fit in 80 columns to match the rest of the > file." I looked at pcie-qcom.c, and with a few minor exceptions, it > fits in 80 columns, and maintaining that consistency makes it easier > to browse. Sometimes exceptions make sense for code, but for > comments, having some that fit in 80 columns and some that require 100 > just makes life harder. > > Bjorn > Sure I will wrap in 80 columns, in my next patch series. - Krishna Chaitanya.